June 27, 2012 -- Cadence Design Systems, Inc. announced today that Ambarella, Inc. realized significant improvements in power, performance and area on a recent 32-nm gigahertz SOC design by upgrading to the latest Cadence Encounter RTL-to-GDSII flow.Using the latest Encounter technology, version 11.1, Ambarella saw a 15% improvement in performance and a 6.4% reduction in power consumption over the prior Cadence technology when designing an encoder/ transcoder SOC.

"The complete Cadence Encounter RTL-to-GDSII flow allowed us to tape out a complex 32-nanometer SOC design and achieve significant and meaningful improvements in power, performance and area," said Chan Lee, Vice President of VLSI Engineering at . "The Clock Concurrent Optimization (CCOpt) technology alone saved us weeks of manual work by allowing us to optimize clocks and datapaths at the same time, while still delivering excellent results in power, performance, and area."

Ambarella was able to concurrently optimize the initial netlist for power, performance and area using RTL Compiler's global-synthesis approach, which enabled a predictable hand-off to EDI System implementation. The new GigaOpt optimization engine inside EDI System produces results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the CCOpt technology unifies clock tree synthesis with logic/ physical optimization, resulting in significant power, performance and area improvements. When joined with the integrated sign-off-proven QRC Extraction and Encounter Timing System, the full benefits of CCOpt timing optimization are maximized by eliminating timing- correlation ECOs, improving time to tapeout.

Posted by: John Miklosz