July 2, 2012 -- S2C, Inc. today announced that Takumi Corp. has implemented a series of graphics IP cores on S2C's rapid FPGA-based prototyping systems including GS3000 and GSV3000 cores. These Takumi IP cores have been fully validated in FPGAs and can be easily demonstrated to and evaluated by designers.

Takumi's GSHARK family of IP is the graphics solution to accelerate display rendering on a variety of embedded systems including mobile devices, digital home appliances and in-car information systems. Designed and customized to support embedded systems, GSHARK-Takumi family extensively lines up graphics IP cores addressing different embedded system use-models, for the best IP selection.

Toshio Nakama, S2C's Chief Executive Officer, said, "Integrating a complex IP core, such as a 3D graphics IP, in a SOC design often requires tremendous amounts of verification effort such as verifying the correctness of all hardware functions, evaluating SOC bus efficiency and testing software compatibilities. And the best methodology today for performing these tasks is by using FPGA-based prototypes that closely resemble the entire design operating at or close to actual speed, many months before actual silicon is available. We've work with Takumi to provide SOC developers a series of advanced graphics IP cores already mapped on FPGA-based prototypes that can significantly shorten IP integration into an SOC design and allow early start of software development and testing."

Takumi's graphics IP cores were prototyped and available as reference designs today on S2C's Virtex-6 760 TAI Logic Modules. The reference designs can be easily ported to the new Virtex-7 2000T TAI Logic Module series or the Altera Stratix-4 820 TAI Logic Module series upon requests. S2C's complete suite of Rapid FPGA-based prototyping solutions is designed to make prototyping easier for designs of any size from 2 million to up to 180 million ASIC gates with 1 to 9 FPGA devices on a single board. In addition, S2C provides a complete solution with prototype-creation and debug software; DPI, SCE-MI and C-API co-modeling; and, a large library of Prototype-Ready IP and accessories.

Posted by: John Miklosz