July 10, 2012 -- Altera Corp. has announced the production availability of its 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores. These cores are effective for building systems requiring very high throughput-rate standard Ethernet connections, including chip-to-optical module, chip-to-chip, and backplane applications.
The media-access-control (MAC) and physical-coding sublayer plus physical-media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba-2010-standard compliant, reducing design complexity for those integrating 40GbE and 100GbE connections on Altera's 28-nm Stratix V FPGAs and 40-nm Stratix IV FPGAs.
With this development, Altera is enabling the system-level throughput promise of 40GbE/ 100GbE and raising the level of design abstraction for FPGA designers, while boosting design team productivity. The 40GbE and 100GbE MAC and PHY IP cores provide an interface consisting of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera's Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05Gbps and 14.1Gbps, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3Gbps.
Altera's 40GbE and 100GbE IP cores are available for separate download from the Altera website and are compatible with the recently announced Quartus II software v12.0.
Go to the Altera Corp. website to find additional information.