July 17, 2012 -- Cadence Design Systems, Inc. announced today that Fujitsu Semiconductor, Ltd. adopted the Cadence Encounter Timing System for timing sign-off after engineers from Fujitsu Semiconductor and Fujitsu VLSI, Ltd., a group company of Fujitsu Semiconductor, completed a comprehensive competitive benchmark across a series of ASIC/ ASSP and SOC designs.

Using Cadence technology, Fujitsu Semiconductor said that 99% of hold violations were resolved after just one iteration through the ECO flow. In addition, negligible impact was made to setup time, and better routability was achieved when compared to another vendor's sign-off product. Cadence Encounter Timing System delivered comprehensive physically aware, multi-mode, multi-corner (MMMC) analysis across the design flow, engineering change orders (ECOs), and final sign-off.

Timing sign-off closure has become an increasingly significant bottleneck due to the increase in modes and corners required for analysis and the divergence of timing results between implementation and sign-off timing tools. Furthermore, the complexity of today's designs requires the ability to do complete physically aware MMMC sign-off during ECO for rapid timing closure. To accomplish this requires a deep integration between physical and sign-off design tools and a fundamentally new approach to software architecture. All of this can be done today uniquely with Cadence Encounter Timing System. The Encounter Timing System's physically aware timing ECO met Fujitsu's qualification criteria, and was incorporated into its production reference design flow.

Cadence Encounter Timing System and QRC Extraction are essential elements within the design-implementation environment. The tight integration between them improves timing convergence throughout the design flow and greatly reduces the time to design closure. While traditional flows require a serial, multi-step iterative process between physical implementation and sign-off, the integrated sign-off technology inside the Cadence digital-implementation flow enabled Fujitsu Semiconductor to reduce the number of ECO loops due to deterministic placement of new cells while optimizing performance and area for its large, high-performance designs.

Posted by: John Miklosz