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Understanding FPGA Processor Interconnects  
Publication: Electronic Design Magazine
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July 17, 2012 FPGAs are wonderful tools. They consist of a collection of logic cells called lookup tables (LUTs) surrounded by an interconnect fabric. The LUTs and fabric are programmable, providing a flexible system that can implement almost any digital algorithm. However, FPGAs offer trade-offs compared to ASICs.

ASICs are more compact and power efficient than FPGAs. FPGA designers have made major improvements in both areas, but a LUT with its configuration storage is simply larger than the logic it will be programmed to implement. Likewise, the interconnect fabric consists of more gates than would be necessary with a direct connection between logic elements.

On the other hand, ASICs are fixed. They can be programmable but at the software level. For example, microcontrollers and microprocessors are essentially standardized ASICs. FPGAs are programmable at the logic level, providing faster, parallel implementations that a processor cannot match. Replacing an ASIC in the field is usually impractical. Reprogramming is common for processor-based ASICs, but there are performance and functional limitations that FPGAs easily exceed.

Programming is the other challenge. Programming or designing logic configurations for an FPGA is significantly different from writing software for a processor. Many high-level FPGA and ASIC design languages such as SystemC are based on the C programming language. But there's a definite mindset for developing FPGA designs using these tools that's not the same for writing applications for a processor.

By William Wong. (Wong is a technology editor for Electronic Design magazine.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Design Magazine website.

Keywords: FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, on-chip interconnect, Electronic Design Magazine
602/38881 7/17/2012 897 108


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