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Xelic Announces 40G I.4/I.7 EFEC Core  
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August 13, 2012 -- Xelic has announced the immediate availability of its XCO23EFEC47 core. This core provides 40G or 4x10G error correction (EFEC) capability that is compatible with ITU-T G.975.1 Appendix I.4 and I.7 and is interoperable with other industry-standard EFEC implementations.

Both the ITU-T G709 I.4- and I.7-compliant schemes provide a higher coding gain (about 7.9dB @ 10-1 BER) than the standard RS(255, 239) (about 5.4dB @ 10-12 BER) for gaussian error distributions while maintaining the standard 7% (16:239) parity:data overhead ratio.

"This core includes both of the leading EFEC solutions for 10G and 40G in a single implementation. This core was designed with a 128-bit datapath and resource sharing is used to provide a very efficient implementation without sacrificing performance," said Mark Grabosky, founding partner and Director of Engineering at Xelic. "This core can be programmed for 4x10G (OTU2) or 40G (OTU3) operation and has support for OTL3.4 statistics. The core is fully compatible with XCO23 40G/4x10G OTN Framer Core and our XCO23AU OTN Multilane interface core which provides OTL3.4 and 4x10 frame-alignment functionality."

In 4x10G mode, the XCO23EFEC47 codec can process 4 streams of OTU2. The XCO23EFEC47 decoder performs bit correction in each individual channel and provides the statistical counts for each stream. Each stream can be independently programmed to perform the I.4 or I.7 algorithm.

In 40G mode, the XCO23EFEC47 codec can process 1 stream of OTU3. The XCO23EFEC47 decoder performs bit correction and provides the statistical counts for both OTU3 data stream as well as OTL3.4.

Posted by: John Miklosz



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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, enhanced forward error correction, EFEC, Xelic,
601/38950 8/13/2012 394 68


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