Page loading . . .

  
 You are at: The item(s) you requested.Tuesday, May 21, 2013
CSR Debuts aptX Low-Latency Codec for Synchronized Audio and Video  
 Printer friendly
 E-Mail Item URL

September 3, 2012 -- CSR, plc has unveiled CSR aptX Low Latency, a new audio-coding technology that slashes to one-third the delay of stereo audio signals over Bluetooth connectivity, effectively enabling consumers to watch video while listening to wireless audio in a synchronized fashion. As a result, the product is ideally suited to wireless audio delivery for video and gaming applications.

CSR aptX Low Latency for Bluetooth offers a coding delay of just 32ms, far less than the standard Bluetooth latency of more than 150ms, and well under the 45ms recommended latency for audio/ video applications.

Although standard Bluetooth technology offers the ability to stream stereo audio wirelessly from mobile handsets and other audio play devices to headphones and speakers, its bandwidth-constrained audio poses inferior sound, and the latency delay is not suitable for video or gaming applications. CSR aptX audio-coding technology is designed to solve both the bandwidth and latency bottleneck, delivering CD-quality sound wirelessly over Bluetooth connections for a variety of consumer electronics applications

Availability

CSR aptX Low Latency is now available for license on CSR audio platforms and on Android OS.

Posted by: John Miklosz



Go to the CSR, plc website to find additional information.

E-mail CSR, plc for more information.

Read more about
CSR, plc
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, codecs, video processing, audio processing, CSR,
601/39073 9/3/2012 480 64


Designer's Mall
0.390625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.46875