As system performance continues to increase the need for higher-bandwidth memory is ever increasing. A novel memory architecture, Quad Band Memory (QBM), that utilizes standard DDR memory devices, a custom PLL, and a "2" to "1" bus switch is introduced. This architecture doubles the available data bandwidth of current DDR SDRAM memory technology.
This paper will present an overview of the design, technical challenges, system tradeoffs, as well as the key methodology features required. Signal integrity and timing are explored in depth while considering inter-symbol interference, reflections, termination, interconnect loss, and populations schemes. Feasibility of this technology at 533-MHz data-rates will be presented.
