As the use of Field Programmable Gate Arrays (FPGAs) continues to become the hardware
design engineer’s choice for implementing custom logic and Intellectual Property (IP), there is an
ever-developing need for the EDA industry to standardize on a common constraint language. This
will not only ensure interoperability between FPGA synthesis and place-and-route tools, but will
allow accurate description of “designer intent” to achieve design closure. Synopsys Design
Constraint (SDC) format has become the industry de facto standard for ASIC designers to
communicate "design intent" to drive synthesis, Static Timing Analysis (STA), placement and verification. With FPGAs now replacing ASICs for many applications, SDC is becoming the
obvious choice for an FPGA design constraint language.
With the advent of constraint-driven synthesis and place-and-route tools, the importance of
accurately describing design performance and implementation requirements through the application
of design constraints has risen dramatically. These tools employ user-defined design requirements
in the form of design constraints and attempt to achieve design closure. An improperly or
insufficiently constrained design can lead to long run times, multiple design iterations and/or
sub-optimal results.
