Mentor Graphics has a large number of white papers and application notes available online. The ones listed below have been selected because they contain useful information that goes beyond the description or use of a particular Mentor Graphics' product. To see all of the white papers and application notes that the company has available, you'll have to go directly to the Mentor Graphics website. You'll also have to register to view any of the white papers or app notes..

SOCcentral Feature Articles
Formal Verification Works Well for Connectivity Checking	3/15/2013
Profiling Defect Sites for Yield Improvement	11/9/2012
3D-IC System Verification Methodology: Solutions and Challenges	7/20/2012
Testing the 3D Waters	7/19/2012
Understanding the Low Power Abstraction	7/6/2012
The Design and Verification Challenge for the Decade	6/14/2012
Using Formal Technology to Improve Coverage Results	4/23/2012
Hardware in the Software Sphere of Influence	3/30/2012
A Verification Methodology for 3D-ICs	10/3/2011
A Third Way in FPGA Development	6/1/2011
Planning Formal Verification Closure	4/20/2011
Boost Verification Quality with Intelligent Testbench Automation	2/23/2011
The Need for a Comprehensive SOC Test Platform	1/16/2011
Seeing Is Believing: How Visualization Simplifies IC DRC	9/1/2010
Low Power: The Next Big Challenge for FPGA Designers	7/12/2010
Advanced Static Verification Is Indispensable	6/7/2010
Evolving Your Organization’s ABV Capabilities	5/17/2010
Realizing ESL with Scalable Transaction-Level Models	5/3/2010
A Look at Emulation vs. Simulation	4/22/2010
The New Standard for 32-nm IC Physical Design and Signoff	3/11/2010
A Practical Approach to Adopting Formal Property Checking	2/10/2010
Automating Advanced Clock-Gating Techniques During High-Level Synthesis	12/10/2009
Accelerate Design Closure with Multi-Core Timing Analysis and Optimization	11/2/2009
What, Why and How of Through-Silicon Vias	10/6/2009
DFM-Compliant IP: Why You Need It, How You Get It	9/9/2009
Protocol Abstraction Views Simplify Chip Interconnect Debugging	9/7/2009
New Flow for Automating Verification of ESD Design Rules	8/3/2009
Reducing IC Power Consumption with Advanced Place-and-Route	6/22/2009
Challenges in 45-nm Physical Design	11/6/2008
Electrical Fuse Makes Repairable Memory Testing Easy	10/5/2008
A Comprehensive Approach to Manufacturing Variability	9/2/2008
What Ever Happened to Formal Verification?	8/5/2008
Art Imitating Life: Hardware Development Imitating Software Development	7/21/2008
Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design	6/9/2008
SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches	4/28/2008
Parasitic Extraction Challenges for Designing Advanced Process ICs	1/9/2008
Creating a Unified Power Flow	11/12/2007
Silicon Validation via LFD Simulation	8/6/2007
Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables	2/2/2007
New Techniques for Testing Communications Devices	11/13/2006
Avoiding Some Common Mistakes When Integrating USB IP Into Your SOC	7/3/2006
Seven Habits of Effective Formal Verification Planning	6/12/2006
Applying Transaction-Level Models for Design and Testbenches	6/5/2006
Transactions for the Masses	5/22/2006
Survey Shines Light on the State of ESL Design	5/8/2006
Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog	3/24/2006
OVL Made Easy for Assertion-Based Verification	2/21/2006
Deflecting the Design Diversity Dilemma: Methods for Improving Mixed-Signal Post-Layout Analysis in an SoC Flow	2/20/2006
FPGA Design Meets the Heisenberg Uncertainty Principle	11/5/2005
EDA Tools Aim at Improving Yield	7/1/2005
Formal Verification with ABV Made Practical	6/1/2005
High Octane ATPG	5/1/2005
Articles Online
Power Verification Is Just as Important as Functional Verification for Complex SOCs	5/14/2013
How to Generate Test Patterns to Detect FinFET Defects	5/6/2013
Boost DFT Efficiency for Large SOCs	4/23/2013
Get More out of System Architectures	1/18/2013
Circuit Reliability Challenges for the Automotive Industry	1/14/2013
Companies Ramp Up to Move from 20nm to the Next Node in 2013	12/18/2012
Emulation Delivers System-Level Power Verification	10/26/2012
Better PCB Design Using the Fabricator's View	10/23/2012
Moving to Advanced Reliability Verification	9/14/2012
Move to Broader Coverage in SOC Verification Metrics	8/16/2012
Separate the Hype from the Reality in 3D-ICs	6/15/2012
Thread Synchronization Techniques for Better Multicore System Power/ Performance Trade-Offs	6/12/2012
Expanding Emulation'S Reach with Virtual Devices	6/3/2012
Effective Finger-Pointing: The Art of Modern Yield Analysis	5/22/2012
Interconnect Modeling at 20nm: More of the Same or Completely Different?	5/10/2012
Design Considerations for Power-Sensitive Embedded Devices	4/17/2012
What's the Difference Between Pre-Layout and Post-Layout PCB Simulation?	3/26/2012
Density Requirements at 28nm	3/12/2012
Understanding Cell-Aware ATPG and User-Defined Fault Models	2/23/2012
Successful Adoption of DFM	2/6/2012
Improving SystemVerilog UVM Transaction Recording and Modeling	1/19/2012
Automating Design Rule Waivers in SOC IP Reuse	12/27/2011
Critical Area Analysis and Memory Redundancy	12/19/2011
Virtual Versus Physical Prototyping: Get It Right Faster	11/28/2011
System Performance Analysis and Software Optimization Using a TLM Virtual Platform	11/22/2011
Assertion-Based Verification Benefits FPGA designs	10/26/2011
Un-Rolling with the Times	9/22/2011
Use Thermal Analysis and Other Types of Simulation to Craft a "Cool" Design	9/16/2011
Cell-Aware Fault Models for IC Production Test Outperform Gate-Exhaustive Fault Models	9/8/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP	9/1/2011
Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels	8/25/2011
Routing Technologies for 28nm and Beyond	8/1/2011
Thermal Analysis and Other Simulation Types	7/27/2011
Are We Ready for Physical Verification Standards?	6/30/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP	6/20/2011
Android, Linux and Real-Time Development for Embedded Systems	6/17/2011
Design Optimization of Flip-Chip Packages Integrating USB 3.0	5/11/2011
Guidelines for Successful SoC Verification in OVM/UVM	5/10/2011
Debugging for Antenna Issues in Copper Processes	5/4/2011
The (Design) House Always Wins: How DFM Improves the Odds of Tape-Out Success	4/1/2011
Automating Design Rule Waivers in SOC IP Reuse	3/31/2011
Attofarad Accuracy for High-Performance Memory Design	3/30/2011
When It Comes to Runtime Chatter, Less Is Best	3/22/2011
The Traditional Approach to IC Implementation and Its Problems	3/11/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 3	3/7/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 2	2/28/2011
Evolution of Manufacturing Closure for Advanced Nodes: Part 1	2/21/2011
Ease Production at 65nm with DFM	2/15/2011
How to Instrument Your Design with Simple SystemVerilog Assertions	1/26/2011
Meeting Timing Specs on Boards with Picoseconds of Margin	1/19/2011
Dawn at the OASIS	1/5/2011
Verification Challenges and eDFM in Digital Designs	1/5/2011
Death to the DRC Waiver Productivity Tax!	1/4/2011
The War Is Over: C++ and SystemC Coexist In a Single Flow	12/15/2010
Automating Rule Sets for Safety-Critical HDL Coding	12/14/2010
Dynamic Memory Allocation and Fragmentation In C and C++	12/9/2010
New IC Verification Techniques for Analog Content	11/17/2010
Essential Principles for Practical Analog BIST	11/4/2010
Power Aware Verification of ARM-Based Designs	11/4/2010
The Future of IC Design Verification	11/1/2010
Booting an RTOS on Symmetric Multiprocessors	9/13/2010
Optimizing the Manufacturing Test Program, Data Collection, and Diagnosis for Yield Analysis	8/31/2010
Reusable Device Simulation Models for Embedded System Virtual Platforms	8/24/2010
Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels	8/16/2010
Give the People What They Want: HLS for RTL Verification	7/21/2010
Android, Linux and Real-Time Development for Embedded Systems	6/28/2010
Clearing the Hurdles of HLS Adoption	4/13/2010
The Multicore SOC: Will 2010 Be the Turning Point?	4/13/2010
Is Semiconductor Industry Consolidation Inevitable?	4/5/2010
Setting Up Hardware Verification Testbenches Using OVM Configuration Classes	4/5/2010
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration	3/22/2010
A Recipe for Verification IP: The Role of Methodology	1/26/2010
Design for Diagnosis to Improve IC Yield	1/25/2010
Deterministic Dynamic Memory Allocation and Fragmentation in C and C++	1/11/2010
Using OVM to Reuse Vital Verification Knowledge	1/5/2010
Easier Cross-Domain Signal Protection for Mixed-Signal SoCs	12/4/2009
FPGA Synthesis Can Be a Leverage Point In Your Design Flow	12/2/2009
FPGA Design and Verification in Mechatronic Applications	10/13/2009
A Guide to C++ for the Cautious Embedded Programmer	6/8/2009
PCB Assembly: An Overview for Designers	5/1/2009
A Power-Aware RTOS Dynamically Balances Performance and Efficiency	4/1/2009
Buy or Build an RTOS: Does It Matter for Medical Devices?	3/28/2009
Manufacturing Compliance: It’s Your Job	3/1/2009
How High-Level Synthesis Can Raise the Efficiency of Design Reuse	2/23/2009
Automating the DDRx Interface Verification Process	1/1/2009
The Role of JTAG in System Debug and Test	10/22/2008
How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 2	5/14/2008
How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1	4/30/2008
Serial ATA and the Evolution in Data Storage Technology	4/28/2008
Virtual Prototyping Boosts Model-Driven Design for Six Sigma methodology, Part 2 of 3: Process Integration Keys Quality	4/17/2008
Guidelines for Using C++ As an Alternative to C in Embedded Designs: Part 2	4/12/2008
Guidelines for Using C++ As an alternative to C in Embedded Designs: Part 1	4/11/2008
Virtual Prototyping Boosts Model-Driven "Design for Six Sigma" Methodology, Part 1 of 3: The Challenges and Tools	4/9/2008
Achieving Yield in the Nanometer Age	12/17/2007
Top-down DSP Design for FPGAs	9/5/2007
Topology Planning and Routing	7/30/2007
How to Enable Microsoft Office and Visio for RTL Design	7/18/2007
Low Power Design Specification from RTL through GDSII	7/9/2007
Capturing and Sharing Intellectual Property in PCB Design	4/19/2007
The New Wave in Functional Verification: Algorithmic Testbench Technology	3/5/2007
Getting the Most Out of ASIC Prototyping with FPGAs	2/7/2007
Getting the Most Out of ASIC Prototyping with FPGAs	2/7/2007
EDA Tools Platforms Increase Productivity in the Nanometer Era	10/19/2006
How to Utilize Advanced FPGA Features without Getting Locked into an Architecture	10/18/2006
Reducing Cycle Times for Design Rule Checking	7/31/2006
A Technical Overview of the CE-ATA Storage Interface	3/20/2006
FPGAs Poised to Play in Embedded Applications	3/17/2006
The "What" and "Why" of Transaction Level Modeling	2/27/2006
Optimizing DSP Functions in Advanced FPGA Architectures	1/25/2006
A Practical Approach to Reusing HDL Code in FPGA Designs	12/28/2005
Using SystemVerilog for Functional Verification	12/5/2005
A Good Methodology Helps Design Teams Check RTL Code	10/27/2005
Test Takes New Role in Yield Improvement	10/17/2005
Advanced Modeling Verifies Backplane Designs	8/15/2005
Intermediate Verification Model Bridges High and Low Levels of Abstraction	8/1/2005
IBIS 4.1 Enhances Signal Integrity Modeling	7/4/2005
The "Why" and "What" of Algorithmic Synthesis	5/2/2005
Guidelines to Maximize the Performance of Verilog-AMS/VHDL-AMS Behavioral Modeling	5/1/2005
A Practical Approach to Design Reuse	4/11/2005
The Rour Rs of Efficient System Design	3/1/2005
Getting to Silicon: Accuracy Requirements of Nanometer Designs	2/17/2005
IP Reuse Simplifies SoC Design, Verification	10/11/2004
Good Bridge Testing Needed	10/4/2004
Adapting ASIC Techniques for FPGAs	9/13/2004
Regression Testing	9/2/2004
Platform-Based Design and Verification with Automated IP Integration	7/12/2004
At-Speed Testing Made Easy	6/3/2004
A New Vision of "Scalable" Verification	3/18/2004
Effective System Verification with a Scalable Verification Methodology	3/17/2004
Design-for-Manufacturing Demands New Infrastructure	1/15/2004
GDSII-based Flow Speeds Mask Data Preparation	1/9/2004
Concurrent FPGA/Board Codesign Ties In	12/8/2003
Rethinking Test at 130 Nanometers and Below	9/12/2003
Using VHDL-AMS to Model Complex Heterogeneous Systems, Part 1	8/21/2003
Using VHDL-AMS to Model Complex Heterogeneous Systems: Part 2	8/21/2003
Managing Loss in High-speed PCBs	7/7/2003
Clock Domain Modeling is Essential in High Density SoC Design	6/6/2003
How Performance Analysis Aids System Design	4/11/2003
Fault Coverage Founders on Speed	3/3/2003

Tutorials, White Papers, etc.

A Methodology for Virtual Hardware/Software Integration

A Unified Approach of PM Noise Cancellation in Large RF Multitone Autonomous Circuits

Achieving Design Closure with Constraint-Driven Synthesis

Advanced Methods for SOC Concurrent Engineering

Beyond P-Cell and Gate-Level Assumptions: Accuracy Requirements for Simulation of Nanometer Designs

Challenges of Silicon Modeling in Nanometer Designs

Co-Verification Enhances Time to Market Advantage of Platform FPGAs

Co-Verification: From Tool to Methodology

Design Integrity Issues Affecting Mixed-Signal Designs

Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning

Efficient Algorithm for Steady-State Stability Analysis of Large Analog/RF Circuits

Eliminating the Problems of Dual Physical Verification Flows

Executing an RTOS on Simulated Hardware Using Co-verification

Fast Functional Verification: Optimum RTL Performance Inside an Integrated, Accelerated Verification Environment

FPGA Synthesis: The Vendor-Independent Approach

FPGAs: Fast Track to DSP

Hardware/Software Co-Verification

Hardware/Software Co-verification of CDMA ASIC Designs

Hardware/Software Co-Verification with RTOS Application Code

IEEE Std VHDL 1076.1-1999: The Analog and Mixed-Signal Extensions for VHDL

Implementing DSP Designs in Altera Stratix Devices

Intellectual Property Business Models

Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration

IP Reuse Creation for System-on-a-Chip Design

LVS - Parasitic Extraction Link: Why Stronger is Better

LVS Automatic Test Vehicles

Managing Design Complexity Through High-Level C-Model Verification

Measuring Physical Parameters: Make Assumptions, Make Mistakes

Modeling Timing Jitter in Oscillators

Noise Considerations in Circuits and Systems

Performance Estimation of MPEG4 Algorithms on ARM based Designs Using Co-Verification

Platform Express Technical Backgrounder

Real Time Operating Systems for FPGA

Reducing FPGA Costs by Saving a Speed Grade

Re-timing for Performance Improvement in FPGA Designs

Simulation Method to Extract Characteristics for Digital Wireless Communication Systems

Smart Move: A Placement-Aware Retiming and Replication Method for FPGAs

Staying Competitive: Advantages of Adopting a Single Tool for AMS SoC Parasitic Extraction

Streamlining the SoC Design Flow

Sun Compute Farms for Electronic Design

Sun Technical Compute Farm (Sun TCF)

Taking Co-verification to the Limit

The "Glue" in a Confident SoC Flow

The Physical Verification Challenge

The Role of C-Based Languages in SoC Flows

The Value of Hardware Emulation

TICER: Realizable Reduction of Extracted RC Circuits

Using Programmable Logic for Embedded Systems

Verification of Radio-Frequency Transceivers

VirtualWires: A Technology for Massive Multi-FPGA Systems

When Does it Make Sense to Design for Reuse?

Who Defines the FPGA Interface?

Webcasts
Physical Verification: The Road Ahead	6/29/2009
Introducing PADS 9.0	6/26/2009
Enterprise Software in Embedded Applications	2/26/2009
Leveraging ESL Techniques To Optimize Low-Power Design	2/13/2008
Inflexion Platform UI: A New Approach to User Interface Creation for Consumer Electronic Devices	3/15/2007
Advanced Design Techniques for FPGAs	6/20/2006
Eliminating Functional Problems Due to Clock-Domain Crossing	5/23/2006
Integrating Functional Formal Verification into a Traditional Flow	5/10/2006

News
Mentor Graphics Accelerates Verification with Emulation-Ready Verification IP for MIPI Products	6/19/2013
Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs	6/10/2013
Mentor Graphics to Provide Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM for Freescale	6/10/2013
SilabTech's 28-nm High-Speed PHYs Delivered Ahead of Schedule with Mentor Graphics Tool Flow	6/10/2013
Mentor Graphics and GlobalFoundries Deliver 20-nm Design Kits for Advanced Design Enablement	6/3/2013
Mentor Graphics and Samsung Optimize 14-nm Process Design Kits	6/3/2013
Atrenta and Mentor Collaborate on SOC Power Sign-off	5/30/2013
Mentor Graphics Brings Seamless Software Trace, Debug, and Performance Analysis to Embedded-Systems Development	5/29/2013
Mentor Graphics and TSMC Collaborate to Improve and Expand 20-nm IC Physical Verification Offering	5/28/2013
Mentor Graphics Design and Verification Tools Certified for TSMC 16-nm FinFET	5/28/2013
Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process	5/22/2013
Mentor and Tezzaron Optimize Calibre 3DStack for 2.5/3D-ICs	5/20/2013
MagnaChip Adopts Mentor Graphics Pyxis Platform and PDK Automation Process	5/14/2013
Mentor Graphics Accelerates SOC and Embedded System Delivery with a Native Embedded Software Environment	4/22/2013
Mentor Graphics' BridgePoint Provides Agilent GC Instrumentation Division an Efficient Methodology for Embedded Software Development	4/22/2013
Mentor Graphics Integrates the MontaVista Automotive Technology Platform into a Yocto Project 1.3 and GENIVI 3.0-compliant Platform	4/22/2013
Mentor Graphics Delivers Simulation and Emulation Solutions to Verify Serial Attached SCSI Products	4/8/2013
Mentor Graphics Announces the First IP-to-System, UPF-based Low-Power Verification Solution	4/4/2013
Mentor Empowers 32-bit MCU Development with Connectivity and Small-Footprint Binary RTOS with Nucleus SmartFit	3/18/2013
TowerJazz Releases Rule Decks for Advanced ESD and Power-Domain Checking Using Mentor's Calibre PERC	3/4/2013
Mentor Graphics Deep Submicron Division Launches the Kronos Cell-Characterization and Analysis Platform	2/27/2013
Mentor Graphics Expands Automotive Linux Infotainment Business	2/21/2013
Mentor Graphics New Questa Verification Platform Functionality Drives Verification Throughput	2/20/2013
Mentor Graphics Announces Availability of xtUML Editor from Open Source Domain	2/19/2013
Mentor Graphics Nucleus Innovate Program Adds NXP Semiconductors and Expands Device Support	2/18/2013
Mentor Graphics Helps NVIDIA Deliver New Microsoft Visual Studio-Based Android Development Platform	2/15/2013
Pure Turns to Mentor Graphics to Develop an Innovative User Interface for Its Pure Avalon 300R HD Digital TV Recorder	2/12/2013
Mentor Graphics Announces New HyperLynx Technology with Advanced 3D-Channel and Trace Modeling, Superior Accuracy and Fast Simulation Performance	1/30/2013
Mentor Graphics Delivers Emulation Solutions for Verification of ARM Cortex-A9 MPCore-based Products	1/21/2013
Mentor Embedded Expands Commercial Linux Development Tools for Freescale QorIQ Devices Based on the Yocto Project	1/8/2013
Mentor Graphics Announces Comprehensive Design Enablement Platform for Samsung's 14-nm IC-Manufacturing Process	12/24/2012
Mentor Enables Smart Device Development for M2M Applications with Support for Zero Configuration Networking	12/20/2012
Mentor Graphics Nucleus Innovate Program Adds Boards from STMicroelectronics to Accelerate Start-Up Development	12/18/2012
HP Deploys Mentor Graphics' Questa CDC	12/17/2012
Mentor Embedded Accelerates High-Performance Signal- and Image-Processing Application Development with Support for MATLAB and ARM Platforms	12/10/2012
Mentor Graphics Verification Academy Launches Coverage Cookbook	11/20/2012
GENIVI 3.0-Compliant Infotainment Product Available from Mentor Embedded	11/19/2012
Mentor Graphics Nucleus Innovate Program Boosts Embedded Development for Start-up Companies	11/15/2012
Mentor Graphics Embedded Linux Platform Achieves Yocto Project 1.3 Compatibility	11/8/2012
ON Semiconductor Completes Multiple Tape-Outs Using Mentor Graphics' Pyxis Custom Router	11/8/2012
Mentor Graphics New Tessent IJTAG Product Automates IP Test and Debug Integration in Large SOC Designs	11/6/2012
Mentor Graphics Delivers Emulation Solutions for the Verification of PCI Express Gen3 Products	11/1/2012
Mentor Graphics Advances Development of High-Performance Multicore Linux-Based Embedded Systems	10/30/2012
Mentor Graphics Sourcery CodeBench Supports Qualcomm Technologies Hexagon Architecture for Embedded Software Development	10/29/2012
Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite	10/24/2012
KALRAY Completes 256-processor, 28-nm SOC Design Using Mentor Graphics Design and Test Tools	10/23/2012
Mentor Graphics Questa Verification Platform Enables Broad Adoption of Formal Verification	10/18/2012
Laker-Calibre RealTime Integration Selected for TSMC Custom Design Reference Flow	10/16/2012
Mentor Graphics Provides Design, Verification and Test Solutions for TSMC's 20-nm Design Infrastructure	10/16/2012
Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC CoWoS Reference Flow	10/15/2012
Mentor Graphics and Teledyne LeCroy Collaborate on Emulation Verification Platform for SuperSpeed USB Applications	10/1/2012
Mentor Graphics Extends UVM Connect to Support OVM	9/10/2012
iD Corporation Adopts Mentor Questa CDC for Clock-Domain-Crossing Verification	8/21/2012
DENSO Adopts Mentor Graphics ICanalyst for Reuse of Analog Circuit Resources	8/20/2012
Mentor's Volcano Network Architect Verifies and Improves Network Bandwidth Usage at Mazda	7/30/2012
Mentor Graphics Announces Support for the Multi-Threaded MIPS32 34K Core with the Nucleus SMP RTOS	7/9/2012
Mentor Graphics Boosts Embedded System Power Efficiency by Extending Power-Management Framework with Hibernate Capability	6/20/2012
Simco Uses Mentor Graphics Inflexion UI to Develop Next-Generation Vehicle Instrument Cluster Human Machine Interface	6/12/2012
Samsung and Mentor Graphics Expand Calibre Sign-Off and Mask-Processing Solution for 20nm	6/6/2012
Hitachi Employs Mentor Graphics' Olympus-SoC Place-and-Route Platform for Critical ASIC Designs	6/5/2012
Mentor Graphics Calibre Pattern Matching Enables Advanced Checking of TSMC 20-nm Designs	6/4/2012
Mentor Graphics First to Support Accellera UCIS with Questa Functional Verification Platform	6/4/2012
Mentor Graphics Receives Certification for TSMC 20-nm Process	6/4/2012
Mentor Graphics Calibre SmartFill Addresses TSMC 20-nm Fill Requirements	5/30/2012
Mentor Graphics and GlobalFoundries Collaborate on 20-nm Fill Solutions Based on Calibre SmartFill	5/29/2012
Mentor DFM Analysis Service Delivers Calibre Litho Checks for TSMC 40-nm and 28-nm Processes	5/24/2012
Mentor Graphics and AT&S Announce Partnership to Optimize PCB Design-Through-Manufacturing Flow	5/24/2012
GlobalFoundries Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC	5/22/2012
SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SOCs	5/22/2012
TowerJazz Finds Unique Solution for Advanced ESD and Power Domain Checking in Calibre PERC	5/22/2012
Vestel Electronics Launches Advanced Set-Top-Box Using Mentor Graphics Inflexion User Interface Technology	5/16/2012
Mentor Graphics Launches Next Generation Veloce2 Emulation Platform with VirtuaLAB Capabilities	4/26/2012
Mentor Graphics and Stonestreet One Announce Integrated Bluetooth Software Stack for Nucleus RTOS Targeting Low-Power, Connected Embedded Development	4/18/2012
Mentor Graphics Moves BridgePoint UML Editor to Open Source Domain	4/17/2012
Mentor Graphics New Questa Platform Functionality Boosts Productivity across the Verification Spectrum	4/16/2012
Mentor Embedded Simplifies Linux and Open-Source Development with Support of the Yocto Project	3/28/2012
Triad Semiconductor and Mentor Graphics Announce Low Cost Mixed-Signal Design with ViaDesigner	3/27/2012
Calibre Flow Developed with Mentor Graphics Consulting Boosts GlobalFoundries Silicon Yield	3/9/2012
Mentor Graphics Signs KETIV Technologies as a Distributor for CAD/ CAM Software and Services	3/7/2012
Mentor Graphics Announces PADS Release Targeting DFM Analysis, High-Speed and Interactive Routing	3/6/2012
Samsung DFM Ready for 20nm Based on Mentor Graphics Calibre Platform	3/2/2012
R.H. Technologies Achieves 80% Downtime Reduction Using Mentor Graphics Valor Manufacturing System Solution	2/27/2012
Mentor Graphics Announces Major New Functionality in HyperLynx Release 8.2	1/30/2012
Altera Adopts Mentor Graphics Veloce Hardware Emulator	1/24/2012
Fujitsu Semiconductor Expands Use of Calibre for Advanced IC Physical Verification and Design-for-Manufacturing	1/23/2012
Mentor Graphics Partners with Freescale to Deliver Vista-Based Virtual Prototype Solution for Freescale Processors	1/13/2012
Mentor Graphics and Ecrio Collaborate to Ready Powerful Nucleus-Based LTE IMS Mobile Device Platforms	1/11/2012
Mentor Graphics Delivers Emulation-Ready Transactors for Accelerated Verification of SOCs	12/19/2011
Mentor Graphics and Mecel Announce the First Complete AUTOSAR 4.x Solution	12/15/2011
Mentor Graphics Announces First Integrated Solution for Component-to-System Thermal Characterization and Analysis	12/13/2011
ZTE Licenses Mentor Graphics Inflexion UI Technology to Develop Advanced 3D Smartphone User Interfaces	12/5/2011
Fujitsu Semiconductor Standardizes on Mentor Graphics HyperLynx Signal-Integrity Technology as LSI-PKG-PCB Co-Design Tool	11/29/2011
Mentor Graphics Android Professional Services Aids Recon Instruments in Developing the First GPS Micro Optics Displays	11/29/2011
Mentor Graphics Integrates Inflexion UI into GENIVI-Compliant Embedded In-Vehicle Infotainment (IVI) Base Platform	11/16/2011
Mentor Graphics Receives TSMC's Partner of the Year Award for 3D-IC Design Enablement	11/14/2011
Mentor Graphics Delivers First ARM Cortex and AMBA Family Verification Solution that Spans Simulation and Emulation	11/11/2011
Mentor Graphics Completes STMicroelectronics 20-nm Test Chip Tape-Out Using Olympus-SoC Place-and-Route System	11/4/2011
Mentor Graphics Veloce Emulator Adopted by ZTE	10/27/2011
Mentor Graphics Delivers Emulation Solutions for the Verification of USB SuperSpeed Products	10/25/2011
Mentor Graphics and MoreThanIP Collaborate to Deliver Veloce Emulation Solutions for Multi-Gigabit Ethernet Verification	10/24/2011
Mentor Graphics Announces the Next-Generation Nucleus RTOS	10/20/2011
Mentor Collaborates with Freescale to Accelerate In-Vehicle Infotainment Product Development for i.MX6 Applications Processors	10/11/2011
Fujitsu Selects Mentor Graphics Sourcery CodeBench for FM3 Microcontroller Family Embedded Development	9/29/2011
Mentor Graphics and NuFlare Technology Extend Collaboration to Address Advanced Maskwriting Challenges	9/20/2011
ARM and Mentor Graphics Define Comprehensive Test Methodology for Arm-Based Designs	9/19/2011
Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality	9/19/2011
Mentor Graphics and TSMC Address Advanced Node Fill Requirements Using Calibre SmartFill	9/15/2011
Mentor Graphics Vista ESL Platform Takes Center Stage in Mentor's ESL Strategy with Expanded Functionality	9/8/2011
Freescale Selects Mentor Graphics to Develop Software Libraries for Enhanced AltiVec Engine	9/7/2011
Mentor Graphics and GlobalFoundries Improve Yield Analysis with Combination of Tessent and Calibre Capabilities	8/30/2011
Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool	8/29/2011
GlobalFoundries and Mentor Graphics Extend Collaboration to Third Generation of DFM	8/29/2011
Mentor Graphics Donates Veloce Emulator to Portland State University	8/22/2011
Mentor Graphics Embedded In-Vehicle Infotainment (IVI) Base Platform Achieves GENIVI Compliance	8/2/2011
Mentor Graphics Announces Comprehensive Embedded Software Development Program for Hardware Companies	7/26/2011
Mentor Graphics Releases Pyxis Custom IC Design Platform	7/25/2011
STMicroelectronics Encourages Fast User-Interface Development for SPEAr Processor with Mentor Graphics Inflexion Technology	7/20/2011
Mentor Graphics Expands Verification Academy Portal with Additional UVM/OVM Content	7/7/2011
Mentor Graphics Announces Embedded Linux Platform Support for Freescale's QorIQ Family of 64-bit Processors	6/23/2011
Mentor Graphics Optimizes Mentor Embedded Inflexion UI for Use on ARM Mali GPUs	6/15/2011
Veridae Systems and Mentor Graphics Partner to Accelerate Development, Debug and Verification of FPGAs	6/8/2011
Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12	6/6/2011
Mentor Graphics Announces Common Embedded Software Development Platform Development from Virtual Prototypes to Hardware Emulation and Boards	6/6/2011
Mentor Graphics Completes 28-nm Physical Design and Verification Flow for GlobalFoundries Technology	6/6/2011
Mentor Graphics Delivers Essential New Capabilities in TSMC AMS Reference Flow 2.0	6/6/2011
Mentor Graphics Mines Design and Test Data to Improve IC Yield and Failure Analysis	6/6/2011
Mentor Graphics Provides Calibre Verification and Tessent Test Solutions for 3D-IC in TSMC Reference Flow 12	6/6/2011
Mentor Graphics Works with Tezzaron and MOSIS on 3D-IC Prototyping Service	6/6/2011
Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping	6/1/2011
Mentor Graphics Partners with TSMC to Validate Advanced Functional-Verification Technology	5/5/2011
Mentor Graphics Announces New Integrated Development Environment Based on the GNU Toolchain	5/3/2011
Mentor Graphics Introduces Eldo Premier Simulator	4/13/2011
Mentor Graphics PCB Design Investment Strategy and Execution Results in 50% Worldwide Market Share	4/11/2011
Mentor Graphics and Carbon Design Systems Partner for Model Distribution	4/5/2011
Mentor Graphics Outlines Strategy for 3D-IC Design, Verification and Testing	3/29/2011
Mentor Graphics Calibre xACT 3D Field Solver Demonstrates High Accuracy and Performance in STARC Evaluation	3/28/2011
Mentor Graphics Teams with TSMC to Enrich Reference Flow 11 Low-Power Verification Solutions	3/28/2011
JEDEC Publishes New Thermal Testing Standard Inspired by Mentor Graphics T3Ster Technology	3/24/2011
Mentor Graphics Delivers Next-Generation Emulation Solutions for Verification of High-Speed Ethernet Products	3/24/2011
Mentor Graphics Tessent YieldInsight Demonstrates Faster IC Failure and Yield Analysis at Fujitsu	3/18/2011
Mentor Graphics Delivers First Multimedia Platform for Hardware Emulation of 3D TV Products	3/14/2011
Mentor Graphics Introduces Calibre RealTime for Instant Sign-off Verification of Custom IC Designs	3/14/2011
SpringSoft's Laker Integrated with Mentor Graphic's Calibre RealTime	3/14/2011
Mentor Graphics Helps CamSemi Replace Design and Verification Flow to Improve Simulation Performance	3/9/2011
Mentor Graphics Announces Logic and Physical Synthesis Support for Xilinx 7 Series FPGAs	3/8/2011
Mentor Graphics and GlobalFoundries Extend RET and OPC Collaboration to 28nm	3/1/2011
Mentor Graphics Hopes to Transform SOC Integration and Functional Verification with Next-Generation Questa Platform	3/1/2011
Mentor Graphics to Join CEA-Leti's IMAGINE Program on Maskless Lithography	3/1/2011
New Shanghai HuaLi Foundry Chooses Mentor Graphics Calibre RET Solution for 65/45-nm Development and Production	2/28/2011
Mentor Graphics Confirms Receipt of Unsolicited Conditional Proposal from the Icahn Group	2/22/2011
Mentor Graphics Underscores Comprehensive Support for UVM 1.0	2/21/2011
Achronix and Mentor Graphics Provide State-of-the-Art Physical Synthesis Support for Speedster22i FPGAs	2/16/2011
MediaTek Adopts Mentor Graphics Calibre PERC as Its ESD and Circuit-Reliability Verification Solution	2/15/2011
VIA Technologies Adopts Mentor Graphics Calibre PERC for Critical ESD Checking	2/7/2011
Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor	1/31/2011
Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability	1/25/2011
STARC Advances Test of Low-Power ICs Using Mentor Graphics Tessent TestKompress	1/24/2011
Mentor Graphics Completes Test Chip with IC Implementation Flow for Common Platform 32/28-nm Technology	1/17/2011
Mentor Graphics and Dongbu HiTek Jointly Release Technology Design Kits for Analog-Intensive BCDMOS Chip Development	1/10/2011
Mentor Graphics Selects 6WINDGate Packet Processing Software for Optimized Multicore Development	1/6/2011
Siemens Expands Its Mentor Graphics Design Environment with Expedition Enterprise and HyperLynx Signal-Integrity/ Power-Integrity Solutions	12/22/2010
Mentor Graphics Joins Linux Foundation	12/15/2010
Mentor Graphics Acquires Certain Assets of CodeSourcery	12/2/2010
Mentor Graphics Teams With Infineon to Deploy State-of-the-Art Verification	12/1/2010
Mentor Graphics and Rohde & Schwarz Deliver a Hardware-Accelerated Debug Platform for Verifying Wireless Communication SOCs	11/22/2010
Mentor Graphics Announces Further Expansion at Broadcom Adopting the Veloce Emulation Platform	11/18/2010
Mentor Graphics Adds NetLogic Microsystems' Multi-Core Processor Support to Mentor Embedded Linux Product Portfolio	11/17/2010
Mentor Extends ReadyStart Embedded Software Platform to TI's Stellaris ARM Cortex-M3 MCUs	11/8/2010
Tuxera and Mentor Graphics Partner to Add exFAT and NTFS Support for Nucleus OS	11/8/2010
Mentor Graphics and ARM Join Forces on Memory Test and Repair	11/1/2010
Mentor Graphics Announces FloTHERM Software With Industry's First Thermal Analysis Bottleneck and Shortcut Innovation	10/25/2010
Mentor Graphics Announces Inflexion Platform User Interface for Android-Based Device Development	10/13/2010
New Mentor Embedded ReadyStart Provides Ready-to-Use Software Platform for Embedded Systems Development	9/22/2010
Mentor Graphics and GateRocket Collaborate on Integrated Solution to Streamline FPGA Verification-Through-Synthesis Flow	9/21/2010
Mentor Graphics DO-254 Platform Adopted By the Civil Aviation University of China (CAUC)	9/14/2010
Mentor Graphics Collaborates With GlobalFoundries to Provide Easier Debugging Capability to IC Designers	8/26/2010
Ricoh Achieves Full Test Coverage With Ultra-Low Pin Count Using Mentor Graphics Tessent TestKompress	8/25/2010
Mentor Graphics Files Patent Infringement Suit Against EVE	8/16/2010
Mentor Graphics Design-to-Silicon Solutions Used in Development of TSMC 28-nm Product-Qualification Vehicle Test Chip	8/11/2010
Mentor Graphics Collaboration with National Instruments Provides Faster Testbench Development	7/26/2010
EnSilica's eSi-RISC Embedded Processors Validated for Mentor Graphics' Precision Synthesis FPGA Design Flow	7/21/2010
Mentor Announces Commercial Linux Platform for Freescale Processors Based on Power Architecture Technology	6/23/2010
Mentor Graphics Questa Functional Verification Platform Adopted by Mindtree	6/21/2010
Mentor Graphics Extends TSMC Reference Flow 11 with Support for ESL and Integrated Design and Manufacturing Closure	6/17/2010
Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB	6/17/2010
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0	6/17/2010
Mentor Graphics Working with TSMC to Speed SOC Verification with Calibre Automatic Waivers	6/11/2010
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology	6/8/2010
Mentor Graphics Underscores Support for OVM and Extends Support to UVM Across Multiple Products	6/7/2010
Mentor Graphics Introduces Precision Rad-Tolerant Product for Advanced Radiation Effects Mitigation	6/3/2010
Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification	6/1/2010
Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More-Complex Designs	6/1/2010
Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release	5/20/2010
Mentor Graphics and NetLogic Microsystems Establish Strategic Multi-Core Collaboration for Embedded Linux	5/19/2010
Valor Releases Major New Functionality In the vSure DFM Product	5/19/2010
Mentor Graphics Veloce Delivers 400X Acceleration for OVM Driven Verification	5/7/2010
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure	5/3/2010
Mentor Graphics and Lauterbach Collaborate On Hardware-Accelerated, Software Development and Debug Platform for SOC Verification	4/27/2010
Mentor Graphics Selected as a Key Freescale Commercial Linux Strategic Partner for QorIQ and PowerQUICC Processors	4/26/2010
Mentor Graphics Announces Multicore Solutions for Symmetric and Asymmetric Multiprocessing	4/22/2010
STMicroelectronics Adopts Mentor Graphics Veloce Emulation Platform for Its New Generation of Set-Top-Box Chip Sets	4/15/2010
Mentor Graphics Extends DO-254 Platform Offering with Enhanced HDL Coding Standards	4/14/2010
Mentor Graphics ReqTracer Automates Requirements Tracking and Reporting for Electronic Design Projects	4/5/2010
Mentor Graphics and Platform Computing Optimize Use of Veloce Emulation Systems as Shared Resources	3/30/2010
SMIC Bases DFM Sign-Off Strategy on Mentor Graphics Calibre Platform	3/30/2010
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine	3/23/2010
The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design	3/23/2010
Mentor Graphics Acquires Valor Computerized Systems	3/18/2010
Mentor Graphics to Extend Cooperation with STMicroelectronics for Advanced Chip-Development Design Solutions	3/16/2010
Mentor Graphics Adds AMBA 4 Verification IP to the Questa Multi-View Verification Components Library	3/10/2010
Mentor Graphics Introduces FloTHERM IC for Semiconductor Package Thermal Characterization and Design	2/25/2010
Dongbu HiTek Adopts Mentor Graphics Eldo for Optimized Cell Characterization Flow	2/23/2010
Mentor Graphics Eases Android Development with Support of Inflexion Graphical User Interface on the Zoom OMAP36x-III Mobile Development Platform	2/15/2010
Mentor Graphics Enhances Signal and Power Integrity Solution with Full-Wave 3D Analysis	2/3/2010
Agnisys Announces Support for OVM Register Package in IDesignSpec	2/1/2010
Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities	1/25/2010
Freescale Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM	1/11/2010
Mentor Graphics Expands Questa Multi-View Verification Components Library to Support a Larger Set of Standard Protocols	12/8/2009
Mentor Graphics Delivers Optimized Android Development System for TI OMAP35x Processors	11/18/2009
Mentor Graphics to Join the SOI Industry Consortium	11/13/2009
Mentor Graphics Outlines Strategy to Unify Silicon Test and Yield Analysis	11/2/2009
New Mentor Graphics Tessent YieldInsight Product Improves IC Yield Through Statistical Analysis of Test Failure Data	11/2/2009
Mentor Graphics Analog/ Mixed-Signal Simulators Enable Widex to Verify Wireless Chip	10/28/2009
Trident Microsystems Adopts Mentor Graphics Veloce Hardware Emulator	10/27/2009
ARM and Mentor Graphics Announce Support for Nucleus RTOS and Nucleus Graphics in the RealView Development Suite	10/22/2009
Mentor Graphics Catapult C Synthesis Selected by Fujitsu QNET to Reduce Power Consumption	10/22/2009
TSMC Selects Calibre Physical Verification Platform for Integrated Sign-off Flow	10/22/2009
Mentor Graphics and Aeroconseil Partner to Support DO-254 in China	10/16/2009
Mentor Graphics to Acquire Valor Computerized Systems	10/14/2009
Mentor Graphics Provides Comprehensive Low-Power Solution in TSMC Reference Flow 10.0	9/21/2009
Mentor Graphics and Applied Materials Deploy OASIS.MASK Open Data Standard for Higher-Efficiency Mask Manufacturing	9/15/2009
Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions for Design and Consulting Services	9/4/2009
Mentor Graphics Launches Precise-IP Vendor-Independent IP Platform for FPGA Design	9/4/2009
Mentor Graphics Veloce Emulation System Adopted by MIPS	9/4/2009
Mentor Graphics Library of Questa Multi-view Verification Components Supports HDMI	8/10/2009
HiSilicon Adopts Mentor Graphics Veloce Hardware Emulator to Accelerate Time-to-Market	8/6/2009
Mentor Graphics Announces Linux and Nucleus Multi-OS Support for Marvell Sheeva Embedded Processors	7/31/2009
Mentor Graphics Announces Nucleus Graphics and Linux Platform for ARM Mali GPUs	7/30/2009
Mentor Graphics Enables Android on Freescale Products Based on Power Architecture Technology	7/30/2009
Mentor Graphics Unveils Android and Embedded Linux Strategy with Acquisition of Embedded Alley	7/30/2009
Mentor Graphics Underscores Low-Power Strategy with Vista Architecture-Level Power Solution	7/29/2009
Mentor Graphics Signs Trident Techlabs as New Distributor in India	7/20/2009
Syntill8 to Offer Mentor Graphics' M8051 Microcontroller IP and Support Services	7/15/2009
Atrenta and Mentor Graphics Collaborate on Power Optimization for High-Level Synthesis	7/14/2009
Mentor Graphics Signs Ruihesoft as New Distributor in China	7/9/2009
Mentor Delivers Hardware-Assisted Solution for Accelerated Verification of Serial-ATA II Products	7/8/2009
Mentor Graphics Extends Catapult C with Support for Control Logic to Enable Full-Chip High-Level Synthesis	6/30/2009
Mentor Graphics Announces Logic and Physical Synthesis Support for Xilinx Virtex-6 and Spartan-6 FPGAs	6/25/2009
UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for Its 65-nm and 40-nm IC Reference Flows	6/24/2009
Mentor Graphics Signs EDA Direct as New Distributor	6/19/2009
Mentor Graphics Delivers PADS 9.0	6/4/2009
Mentor Graphics Announces All-Calibre Physical Verification and DFM Flow for Advanced IC Designs at Fujitsu Microelectronics	5/27/2009
Mentor Graphics Delivers HDTV Platform for the Accelerated Verification of HDMI and DisplayPort Products	5/15/2009
NXP Adopts Mentor Graphics' Veloce Hardware Emulator for Its HDTV and Set-Top-Box Chipsets	4/16/2009
Mentor Graphics Unveils New Low-Power Features in Olympus-SoC Place-and-Route Platform	4/7/2009
Mentor and NXP Achieve Major Milestone in Silicon Test Partnership	3/27/2009
Mentor Graphics Provides Complete 3D Variability Solution Addressing Density and Thickness Challenges	3/18/2009
Mentor Graphics Precision Synthesis Tool Family Supports Altera's Stratix IV GT and Arria II GX FPGAs	3/9/2009
Mentor Graphics Eldo Simulator Used by STMicroelectronics to Characterize 32-nm Cell Libraries	3/6/2009
Selete Selects Mentor Graphics Calibre nm Platform for EUV Flare Compensation	2/27/2009
Mentor Graphics inFact Tool Provides Plug-and-Play Interoperability with OVM	2/10/2009
Mentor Graphics Delivers Power Integrity Analysis for Advanced PCB Systems Design	2/4/2009
Mentor Graphics and Achronix Semiconductor Extend Synthesis Support for Achronix Field Programmable Gate Arrays	1/27/2009
Mentor Graphics and Freescale Expand Collaboration to Improve Manufacturing and Testing of Nanometer Technologies	1/27/2009
STMicroelectronics Adopts Mentor Graphics DFT Tools for Advanced IC Testing	1/26/2009
Mentor Graphics Completes Acquisition of Agility Design Solutions C Synthesis Suite	1/23/2009
Mentor Graphics Announces Scalable TLM-2.0 Design Flow Using Vista and Catapult C Synthesis ESL Design Tools	1/21/2009
Mentor Graphics Supports Fujitsu to Implement Open Verification Methodology (OVM)	1/19/2009
IPextreme Teams with Mentor Graphics on 8051 Cores	1/13/2009
Mentor Graphics Quadruples Veloce Hardware Emulation Capacity to a Half Billion Gates	12/16/2008
Mentor Graphics Olympus-SoC Place-and-Route System Qualifies for TSMC 40-nm Processes	12/11/2008
Mentor Graphics Announces Capital Architect for Dynamically Optimizing the Physical Architecture of Vehicle EDS Systems	12/10/2008
Mentor Delivers Solution for SystemVerilog Base Class Library Interoperability to Enable Reuse of Legacy VMM Code in an OVM Environment	12/5/2008
NEC Electronics Selects Mentor Graphics Calibre nmLVS for Circuit Characterization at 40nm and Below	11/14/2008
Forty CAST IP Cores Validated for Mentor Graphic’s Precision FPGA Synthesis Tool	11/13/2008
Mentor Graphics Collaborates with Lake Washington Technical College to Open PCB Design Laboratory	11/13/2008
Teradyne and Mentor Graphics Partner to Provide Yield Learning Solution for Nanometer Geometry Devices	11/7/2008
Mentor Graphics Boosts Eldo Simulator Performance with Generalized Multi-Threading Technology	11/5/2008
Mentor Graphics Broadens Support of OVM Compliant Verification IP for IEEE802.3-2005 Gigabit Ethernet-based Designs	10/31/2008
Mentor Graphics Announces Nucleus Platform Media Player for Rapid Delivery of Multimedia Applications	10/28/2008
Teseda and Mentor Graphics Partner to Speed Defect Diagnosis	10/27/2008
Mentor Graphics Veloce Deployed by Mitsubishi to Deliver High-Quality HDTV Video Decoder Chip	10/16/2008
Mentor's Olympus-SoC Place-and-Route System Slashes Design Closure Times with Parallel Timing Analysis and Optimization Technology	10/13/2008
TSMC Adopts Mentor Graphics Calibre Equation-Based DRC Feature for Advanced Physical Verification	10/8/2008
Infiniscale and Mentor Graphics Collaborate with STMicroelectronics to Offer a Design Solution for Analog Parametric Yield Optimization	9/25/2008
Mentor Graphics Announces Precision Synthesis Support for New Xilinx Virtex-5 TXT FPGAs	9/25/2008
Mentor Graphics and PTC Deliver Bi-Directional ECAD-MCAD Collaboration Capability	9/19/2008
IBM and Mentor Graphics to Develop 22-nm Computational Lithography Solution	9/18/2008
AWR and Mentor Graphics Unveil High-Frequency PCB Co-Design that Obsoletes File Translation	9/17/2008
New Release of the OVM Takes Verification to the Next Level	9/12/2008
Mentor Graphics Veloce Deployed by Mitsubishi for High-Quality HDTV Video Decoder Chip	9/2/2008
Mentor Graphics and Altera Partner on DO-254	8/20/2008
Mentor Graphics Responds to Cadence Announcement of Withdrawal of Acquisition Proposal	8/18/2008
Mentor Graphics Eldo Adopted by TSMC for Cell Library Characterization of 40-nm	8/13/2008
BitSim joins Mentor Graphics's Questa Vanguard Program	8/8/2008
Mentor Graphics Delivers Simulation for Automotive and Aerospace Electrical Systems Designers in CHS 2008.1 Release	7/29/2008
Mentor Consulting Slashes Time-to-Mask at Dongbu HiTek with Optimized Calibre Flow	7/24/2008
Mentor Donates Unified Coverage Database to the Accellera Unified Coverage Interoperability Standard Technical Subcommittee	7/21/2008
Mentor Graphics Achieves Industry-First OpenMAX Conformance for Nucleus OS Multimedia Framework	7/17/2008
Mentor Graphics Announces Support of Model-Driven Design for Six Sigma in the Automotive Industry	7/17/2008
Magma's Knights Camelot CAD Navigation Solution Now Links to Mentor Graphics YieldAssist Fault Diagnostic Engine	7/15/2008
Mentor Graphics Enhances inFact to Exploit Distributed Compute Environments	6/27/2008
Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of PCI Express Applications	6/26/2008
Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of Multimedia Applications	6/19/2008
Mentor Graphics Rejects Proposal from Cadence Design Systems	6/17/2008
Mentor Graphics Responds to Proposal from Cadence Design Systems	6/17/2008
Mentor Graphics Expands Nucleus Platform Solutions to Freescale i.MX31 Processor for Multimedia Applications	6/16/2008
Mentor Graphics Provides Advanced Design For Manufacturing Capabilities in TSMC Reference Flow 9.0	6/13/2008
Mentor Graphics Outlines IC Implementation Strategy to Address Sub-45nm Challenges	6/10/2008
Mentor Graphics Qualifies Calibre Model-Based Planarity Flow for TSMC's 65- and 40-nm Processes	5/30/2008
Toshiba Selects Mentor Graphics Calibre DFM Platform for its Device Extraction Flow	5/20/2008
Mentor Graphics Supports Altera's Stratix IV FPGA Device Family for 40-nm Design Applications	5/19/2008
Mentor Graphics Acquires Assets of Ponte Solutions; Technology to be Integrated into Calibre DFM Solutions	5/16/2008
UMC and Mentor Graphics Introduce Foundry Design Kits (FDK) for Mixed-Mode and RF Technologies	5/14/2008
Mentor Graphics Aligns Product Groups to Address IC Implementation Challenges at 45nm and Beyond	5/8/2008
Mentor Graphics Announces Partnership with NXP Semiconductors for Design-for-Test Tools and Technology	5/7/2008
Mentor Graphics Aligns with UMC to Validate the Accuracy of Calibre nmDRC Physical Verification UMC 65-nm Deck	4/30/2008
Mentor Graphics Accelerates "Smart" User Interface Innovation with Nucleus Software Platform for Atmel Microcontrollers	4/16/2008
Mentor and Agilent Announce EDA Integrated Solution for RF-PCB Development	4/8/2008
Mentor Graphics Announces Synthesis Support for Xilinx Virtex-5 FXT FPGAs	4/1/2008
Mentor Graphics Expands Questa Functional Verification Platform	3/27/2008
STARC Establishes Variation-and-Yield-Aware Design Methodology Using Mentor Graphics Calibre LFD	3/27/2008
Mentor Graphics Platform Express Now Supports IP-XACT 1.4 Specification from the SPIRIT Consortium	3/19/2008
Mentor Graphics Calibre nmOPC on Cell/B.E. Platform Qualified for Production at IBM	2/26/2008
ProDesign and Mentor Graphics Sign OEM Agreement	2/19/2008
Mentor Graphics Delivers Breakthrough in Verification Intelligence	2/18/2008
Cadence and Mentor Enhance Open Verification Methodology	2/14/2008
Mentor Graphics Releases Updated Serial ATA Host and Device Controllers for Storage Applications	1/25/2008
Mentor Graphics Announces Catapult C Synthesis Accelerated Libraries for Xilinx Virtex-5 FPGAs	1/22/2008
Mentor Graphics Delivers Physical Synthesis Solution for Altera Stratix III Device Family	1/18/2008
Mentor Graphics Nucleus OS Offers Seamless User Experience for Multimedia Devices	1/16/2008
Mentor Graphics and Calypto Announce ESL Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker	1/14/2008
Mentor Graphics Precision Synthesis Combined With Xilinx SmartGuide Technology Dramatically Reduces Design Time	12/12/2007
Mentor Graphics Announces Multi-mode Multi-Corner Signal Integrity Solution for 65/45nm	12/10/2007
Toshiba Information Systems Adopts Catapult C Synthesis for Next-Generation ASIC Design	12/4/2007
Mentor Graphics Questa Functional Verification Platform Adopted by Siemens IT Solutions and Services PSE	12/3/2007
Mentor Graphics Olympus-SoC Place and Route System used by STMicroelectronics to Tape Out Set-Top Box Chip	11/27/2007
Mentor Graphics Announces an Optimized FPGA Design Flow Between Precision Synthesis and MathWorks Simulink HDL Coder	11/15/2007
Mentor Graphics and TSMC Collaborate to Release 65-nm RF Design Kits	11/13/2007
Mentor Graphics Announces HDL Designer Series with SystemVerilog Support for Design-to-Verification Productivity	11/7/2007
Mentor Graphics Joins Multicore Association as Executive Board Member	11/6/2007
Mentor Graphics and Avery Design Team to Deliver Comprehensive PCI Express and Serial ATA IP Solutions	11/5/2007
Mentor Graphics and LeCroy Collaborate to Deliver High-Performance Verification Platform for USB Applications	11/1/2007
Elektrobit Selects Catapult C Synthesis to Design Next-Generation Wireless Hardware	10/24/2007
Mentor Graphics Releases Serial ATA PHY Intellectual Property for SMIC 130-nm Generic Process	10/23/2007
Mentor Graphics and Altera Announce Catapult C Synthesis Accelerated Libraries for High-Performance DSP Hardware in FPGA	10/12/2007
Mentor Graphics Announces TestKompress Xpress Technology to Address Manufacturing Test Requirements for 65- and 45-nm ICs	10/1/2007
Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis	9/24/2007
Mentor Graphics Accelerates FPGA/PCB Design Collaboration with New I/O Designer Product Targeted at PADS Users	9/19/2007
Mentor Graphics Introduces Multimedia Solution for Nucleus OS and Inflexion Platform	9/19/2007
MediaTek Adopts Mentor Graphics Formal Verification Technology for Next Generation Designs	9/18/2007
Mentor Graphics Offers PCI Express Controller and AMBA Bridge Intellectual Property Solutions	9/5/2007
Mentor Graphics Offers Sonics SMART Interconnect Solutions	8/22/2007
Mentor Graphics Announces Nucleus OS and EDGE (Eclipse) Developer Suite for the IBM Cell Broadband Engine Processor	8/21/2007
Cadence and Mentor Graphics to Standardize on Open SystemVerilog Verification Methodology	8/16/2007
Mentor Graphics Delivers Verification Solutions for ARM-based Wireless and Multimedia Applications	6/26/2007
Volvo Trucks and Mentor Graphics Successfully Complete AUTOSAR Project	6/18/2007
Mentor Graphics Acquires Sierra Design Automation	6/11/2007
Mentor Graphics Collaborates with TSMC to Provide Advanced DFM Capabilities in Reference Flow 8.0	6/5/2007
Mentor Graphics' DFM Solution Qualified by Common Platform Technology Alliance for 45nm and 65nm	6/4/2007
Chartered and Mentor Graphics Team to Offer Technology Design Kits for 65- and 90-nm Common Platform Technology Processes	5/31/2007
Denali and Mentor Team to Enable Verification IP for SystemVerilog Verification Environments	5/31/2007
Mentor Graphics Introduces Small Footprint, Industry-Compliant Serial ATA PHY for Optimized Low-Power Designs	5/25/2007
Mentor Graphics and UMC Deliver Analog Mixed-Signal Reference Flow	5/23/2007
Mentor Graphics and Fujitsu Collaborate to Provide Calibre LFD Solution for Fujitsu's Internal and Fabless Customers	5/22/2007
Yogitech Selects Mentor Graphics' Platform Express to Deliver IP-XACT Descriptions for Merchant IP Products	5/22/2007
UMC Expands Support for Mentor Graphics' Calibre YieldAnalyzer to Deliver Production Proven DFM Flow	5/15/2007
Mentor Graphics Expands Questa Functional Verification Platform and Targets Low-power Designs	5/14/2007
STARC to Use Mentor Graphics TestKompress ATPG Tool to Target Delay Defects	5/9/2007
Agilent Technologies Announces Strategic Partnership with Mentor Graphics on Automotive Network Design, Test and Validation Tools	5/8/2007
Mentor Graphics Announces Synthesis Support for New Altera Arria GX FPGA Family	5/8/2007
Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology	5/8/2007
Magma and Mentor Graphics Demonstrate Interoperability of UPF-Compliant Implementation and Verification Flow	4/16/2007
Mentor Graphics Launches Veloce Product Family	4/16/2007
Mentor Graphics Announces Synthesis Support for Xilinx Spartan-DSP Series	4/3/2007
Mentor Graphics Extends Inflexion Platform User Interface for the Nucleus Operating System	4/2/2007
Mentor Graphics Provides Comprehensive Product Support for New ARM Cortex-M1 Processor for FPGAs	3/29/2007
Mentor Graphics Announces Subsystem Intellectual Property Launch with First Delivery of Integrated USB Solution	3/26/2007
iVivity Selects Mentor Graphics Ethernet IP Family for iDiSX State Machine Architecture	3/21/2007
Mentor Graphics Announces Synthesis Support for New Altera Cyclone III FPGAs	3/19/2007
New Mentor Graphics Nucleus USB Class Driver Supports Firmware Upgrades	3/13/2007
Mentor Graphics Provides Co-Verification Support for MIPS32 34K Multi-Threading Processor Cores	3/12/2007
Mentor Graphics Announces Synthesis Support for Xilinx Virtex-5 SXT FPGAs	3/8/2007
Mentor Announces PADS2007 with Major Technology and Productivity Enhancements	3/6/2007
Panasonic Mobile Communications Adopts Catapult SL for Next-Generation Chip for Communication Infrastructure Equipment	2/9/2007
Mentor Graphics Delivers Next-Generation Board Station Flow	2/6/2007
Mentor Graphics Collaborates with TI to Use Nucleus OS Mobile for Affordable Multimedia Handsets	2/2/2007
Sun Microsystems and Mentor Graphics Collaborate to Provide Solaris 10-based EDA Solutions on x64 Platforms	1/30/2007
STARC Standardizes on Calibre YieldAnalyzer as Reference Tool in DFM Flow for Critical Area Extraction	1/26/2007
Mentor Graphics Nucleus I2C Software Helps Integrate On-Board Devices	1/18/2007
Actel and Mentor Graphics Expand Partnership	1/16/2007
eInfochips Supports Mentor Graphics' Questa Vanguard Program for AMBA AHB SystemVerilog Verification Component	12/18/2006
Cypress Adopts Mentor Graphics Calibre xRC for Parasitic Extraction	12/14/2006
Mentor Graphics Calibre xRC and Calibre xL Tools Validated for TSMC 65-nm Process Technology	12/14/2006
Mentor Graphics Introduces Advanced User Interface Capabilities for High-Volume Mobile Phones and Consumer Electronic Devices	12/6/2006
Ciranova and Mentor Graphics Demonstrate Interoperability Benefits of OpenAccess-Based PCell Solutions	12/5/2006
Mentor Graphics Announces Synthesis Support for Xilinx Spartan-3A FPGAs	12/5/2006
Mentor Graphics Introduces High-Speed USB-Certified PHY for Embedded Host Applications in the SMIC 0.13-µm Process	12/5/2006
AMCC Standardizes on Mentor Graphics' Questa Platform, Advanced Verification Methodology (AVM), and SystemVerilog	11/30/2006
Mentor Graphics and TSMC Provide TSMC-Qualified Process Design Kit for 0.13-Micron Mixed-Mode and RF Design	11/30/2006
Mercury Computer Systems Partners with Mentor Graphics and Develops First Cell BE Processor-Based Platform for EDA Market	11/30/2006
Mentor Graphics Releases Next-Generation OPC Solution	11/29/2006
Faraday Adopts Mentor Graphics TestKompress	11/13/2006
Mentor Graphics Announces Synthesis Support for New Altera Stratix III FPGAs	11/8/2006
Mentor Graphics HyperLynx 7.7 Introduces New SerDes Technology and Major Productivity Enhancements	10/31/2006
Mentor Graphics Strengthens ESL Offering with Acquisition Of Summit Design	10/24/2006
Mentor Graphics TestKompress 2007 Improves on Productivity, Performance, and Test Quality	10/23/2006
Mentor Graphics YieldAssist Supports Automated, Server-based Use Model for Rapid Yield Learning	10/23/2006
Mentor Graphics Announces Synthesis Support for Xilinx Virtex-5 LXT FPGAs	10/18/2006
Mentor Graphics Announces Ford Is Standardizing on the CHS Electrical Design Tools	10/17/2006
Mentor Graphics Solves Key Industry Challenges with New CHS Wire Harness Design Tool	10/16/2006
LG-Nortel's Key Telephone Team Standardizes on Nucleus IPv6 and Gains TTA's IPv6 Certification	9/26/2006
Mentor Graphics Eases Software Development Tool Cost Issue with EDGE Development Suite	9/26/2006
Mentor Graphics' New Topology Router Technology Revolutionizes Layout Process for Manually Designed PCBs	9/25/2006
Mentor Graphics Upgrades Nucleus PLUS RTOS Software to Provide Easier Portability, Faster New Hardware Support	9/25/2006
Mentor Graphics Collaborates with Budapest University of Technology and Economics to Open Chip Design Laboratory	9/22/2006
Mentor Graphics Donates Power Configuration File Format to the Accellera Unified Power Format Technical Subcommittee	9/19/2006
Mentor Graphics Calibre OPCverify Selected by Matsushita for Manufacturing Verification of Nanometer Technologies	9/18/2006
Agere Systems' Storage Division Readies for 65-nm with Adoption of Mentor Graphics Calibre	9/13/2006
Cswitch Adopts Mentor Graphics 10 Gigabit Ethernet MAC for Configurable Switch Array Chip	9/13/2006
Jazz Semiconductor and Mentor Graphics Release Comprehensive Design Kits for Analog/Mixed-Signal Integrated Circuit Design Flow	9/5/2006
Haier IC Adopts Mentor Graphics Eldo Simulator as the Standard Tool for Analog Circuit Design	8/23/2006
Mentor Graphics to Deliver Select EDA Technologies to Freescale Semiconductor	8/14/2006
MediaTek Adopts Mentor Graphics Clock-Domain Crossing Methodology for Digital Media Integrated Chipsets	8/11/2006
Fujitsu Microelectronics Solutions Selects Mentor Graphics Catapult Synthesis for Wireless Communication Applications	8/2/2006
Mentor Graphics Delivers First Hardware/Software Processor Support Package for the ARM Cortex-M3 Processor	8/1/2006
Mentor Graphics and ARM Validate Physical IP for Robustness to Lithographic Variation Using Calibre LFD	7/28/2006
Mentor Graphics Calibre nmDRC Adopted for Sign-Off by UMC	7/28/2006
Mentor Graphics Calibre nmDRC Delivers Superior Productivity on the Intel Dual-Core Xeon 5160 Processor	7/28/2006
Mentor Graphics Calibre nmDRC Supports the AMD Opteron Processor	7/28/2006
Mentor Graphics EDGE Tool Suite Supports Freescale ColdFire Microprocessors and Microcontrollers	7/28/2006
Nucleus RTOS and EDGE Tools Now Available for Developers of Wireless Mobile Devices Using Freescale's i.MX31 Applications Processor	7/28/2006
TSMC Qualifies Mentor Graphics Calibre nmDRC on 65-nm Process	7/28/2006
Sierra Design Automation Collaborates with Mentor Graphics to Enable Lithography-Driven Closure for 65-nm and 45-nm Designs	7/19/2006
Mentor Graphics Integrates the Newly Acquired ADiT Fast-Spice Technology with ADVance MS	7/12/2006
Mentor Graphics Redefines DFM Handoff with Calibre nmDRC, Part of New Calibre nm Platform	7/12/2006
Mentor Graphics Announces New Bit-Accurate C++ Datatypes that Accelerate Algorithm Validation by 10X	6/27/2006
Mentor DFT Tools Fully Support TSMC's Reference Flow 7.0	6/21/2006
Mentor Graphics Introduces High-Level Synthesis Tool to Create High-Performance Subsystems from Pure ANSI C++	6/12/2006
Pioneer Chooses Mentor Graphics Catapult C Synthesis Tool for R&D of Digital Signal Processing Applications	5/23/2006
Mentor Graphics Adds Transient Simulation Capability to CHS	5/19/2006
Mentor Graphics Calibre Platform Provides Integrated DFM Flow for TSMC 65-nm Technologies	5/17/2006
Mentor Graphics Announces Synthesis Support for Xilinx Virtex-5 FPGAs	5/15/2006
Enuclia Standardizes on Mentor Graphics Calibre Platform for Physical Verification and Parasitic Extraction of its New DTV ASIC Designs	5/12/2006
Mentor Graphics Announces Integrations with Key UGS Products and Streamlines the Electro-Mechanical Product Development Process	5/12/2006
Mentor Graphics Unveils Next Generation of Functional Verification	5/9/2006
Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem	5/8/2006
Newest Release of Mentor Graphics' Platform Express Supports SPIRIT Consortium's New Specification	5/2/2006
Mentor Graphics Verifies Clock-Domain Crossing Solution for Sun Microsystems UltraSPARC T1 Processor	4/25/2006
Mentor Graphics Opens Design Laboratory at Russian University	4/20/2006
Mentor Graphics' XtremeAR Reduces Auto-Routing Times on Large PCBs from Days to Hours	4/11/2006
Mentor Graphics' EDGE Tool Suite Earns the Synchromesh Computing Validation and Seal of Approval for Freescale's i.MX Processor Family	4/10/2006
Mentor Graphics Calibre Tools Strengthen DFM Flow for IBM/Chartered/Samsung 65-nm Common Platform Technology	3/31/2006
Mentor Graphics Enables Seamless Migration to PADS PCB Design Solution with Release of New Translators	3/29/2006
Mentor Graphics Unveils New Calibre Litho-Friendly Design Product, Bringing Process Variability Data into the Design Flow	3/6/2006
Mentor Graphics' Seamless Named Premier Co-Verification Tool for new Tensilica Diamond Series Processors	2/22/2006
Mentor Graphics Calibre Mask Data Preparation Ready for 45nm	2/16/2006
Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models	2/7/2006
Mentor Graphics and STARC Partner to Develop Improved at-Speed Test Methods for Nanometer Design	1/25/2006
Mentor Graphics Provides Platform Express Solution for LSI Logic RapidChip Platform ASIC Partner Program	1/18/2006
Mentor Graphics Collaborates with AMD to Deliver PCB Reference Designs	1/17/2006
MediaTek Adopts Mentor Graphics Eldo for Its Library Characterization	1/13/2006
Faraday Adopts Mentor Graphics Eldo as Its Internal SPICE Simulator	1/12/2006
Mentor Graphics Next-Generation OPC Technology Ensures Yield Across Manufacturing Process Window	1/9/2006
SMIC Adopts Mentor Graphics Eldo Simulator for Analog Circuits for its 0.13-µm and Below Process Nodes	1/6/2006
QuickLogic Moves to Precision Synthesis; Signs Multi-Year OEM Agreement with Mentor Graphics	12/28/2005
AMI Semiconductor and Mentor Graphics Partner to Offer Mixed-Signal Technology Design Kit for Foundry Customers	12/19/2005
Mentor Graphics Announces Calibre Encryption Technology Adopted by IBM	12/19/2005
austriamicrosystems Releases New Version of Design Kit for Latest Mentor Graphics' IC Design Flow	11/30/2005
Mentor Graphics Expands DFM Strategy with YieldAssist Diagnostics Tool for Yield Improvement	10/31/2005
QuickLogic Lowest-Power FPGAs Supported by Mentor's Precision Synthesis	10/31/2005
Mentor Graphics Releases Expedition Enterprise PCB Systems Design Solution	10/26/2005
New Synfora PICO Express Interface to Mentor Graphics ModelSim Simulation Environment Now Available	10/17/2005
Mentor Graphics Announces Comprehensive Portfolio of Automotive Electrical/ Electronic Design Tools	10/6/2005
Mentor Graphics Seamless Product Supports Next-Generation PowerQUICC III Communications Processor from Freescale	9/7/2005
Mentor Graphics Calibre Extracted View Interface Completes Integration to Cadence Design Creation Environment	8/30/2005
Mentor Graphics Partners with China Academy of Science to Build System Design Lab	8/23/2005
Mentor Graphics HyperLynx Enables Easy Implementation of Multi-Gigabit, SERDES Interconnect Technology	8/15/2005
Mentor Graphics Introduces over 140 Enhancements to Capital Harness Systems Suite	8/11/2005
Mentor Graphics Enables PCB Design Companies to Comply with Hazardous Materials Regulations	7/26/2005
Mentor Graphics Receives Industry Certification of ULPI Support for USB On-the-Go IP Core	7/21/2005
ASUS Adopts Mentor Graphics Printed Circuit Board Tools	7/8/2005
Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL	6/2/2005
Siemens Chooses Mentor Graphics as Global EDA Partner in Multi-Tool Agreement	6/2/2005
Mentor Graphics Achieves PCI Express Intellectual Property Compliance on NitAl Platform	5/26/2005
Mentor Graphics Strengthens Its Automotive Solutions Portfolio with Acquisition of Volcano Communications Technologies	5/26/2005
Sanyo Selects Mentor Graphics Catapult C Synthesis for Next-Generation Multimedia LSI Design	5/25/2005
Stretch Licenses Mentor Graphics 10/100/1000 Mbps Ethernet MAC IP	5/25/2005
Mentor Graphics Attacks Verification Bottlenecks with New Questa Verification Products	5/16/2005
Mentor Graphics Announces Certification of Its High-Speed USB On-The-Go Controller IP	5/13/2005
FishTail Joins Mentor Graphics' OpenDoor Program and the ModelSim Value Added Partnership Program	5/11/2005
OCP-IP Announces Availability of Mentor Graphics CheckerWare Library of Verification IP	5/10/2005
Mentor Graphics and LSI Logic Announce Seamless Product Support for ZSP Processor Cores	5/4/2005
Mentor Graphics Extends Catapult C Synthesis Product	5/2/2005
Mentor Graphics Joins CE-ATA Group and Begins Storage IP Development Based on New 1.0 Specification	4/19/2005
Mentor Graphics Configurable Port is Compliant with the PCI Express Specification	4/13/2005
Xilinx Uses the Precision Synthesis Tool from Mentor Graphics in its Advanced FPGA Design Training Courses	4/4/2005
Accellera Accepts Mentor Graphics' Donation of SystemVerilog Assertion Version of the Open Verification Library	3/30/2005
Mentor Graphics' Integrated Constraint Entry System Facilitates High-Productivity Team Design of PCB Systems	3/28/2005
UMC Adopts Mentor's TestKompress Embedded Compression Solution for Manufacturing Test	3/24/2005
Renesas Electronics Integrates Mentor Graphics 0-In Assertion Synthesis for Assertion Based Verification Flow	3/22/2005
PADS2005 Provides Productivity and Ease-of-Use Enhancements for PCB Systems Designers	3/10/2005
Fraunhofer IIS Selects Mentor Graphics Catapult C Synthesis for Advanced Signal Processing Applications	3/8/2005
Mentor Graphics Collaborates with VIA to Deliver PCB Reference Designs	3/1/2005
Mentor Graphics Joins ProSTEP iVip Forum to Facilitate Automotive Electrical Standards Development	2/22/2005
LSI Logic licenses Ethernet MAC Core from Mentor Graphics	2/15/2005
Worldwide EDA Tech Forum Series Starts on March 16	2/14/2005
Mentor Graphics Announces Synthesis Support for HardCopy II Structured ASIC Devices	1/25/2005
Mentor Graphics Announces Synthesis Support for ProASIC3 and ProASIC3/E Families	1/25/2005
TSMC Validates 90nm Process Technology with Mentor Graphics Calibre xRC Test Chip Program	1/12/2005
Mentor Graphics Adds Advanced Design Capabilities for Flex and Rigid-Flex Boards	12/20/2004
Mentor Graphics Announces Platform Express Product Support for the new SPIRIT 1.0 Specification	12/8/2004
Mentor Graphics Joins Serial ATA International Organization	12/8/2004
Mentor Graphics Delivers Analog Mixed Simulator to NEC Electronics	11/23/2004
Adoption of Verilog-AMS Language Design at Toshiba Aided by Mentor Graphics' ADVance MS Tool	11/17/2004
Mentor Graphics Announces New iSolve High Performance Verification Speed Adapters for USB and PCI Express Protocols	11/16/2004
Mentor Graphics and Xilinx Collaborate to Cut Design Time, Optimize Performance for Integrated FPGA-on-Board Designs	11/10/2004
Atmel Broadens Partnership with Mentor Graphics with OEM Agreement Spanning Synthesis, Simulation and Verification	11/9/2004
Magma and Mentor Graphics Announce TestKompress Integration into RTL-to-GDSII Flow	10/25/2004
Lattice Semiconductor and Mentor Graphics Extend and Expand Partnership	10/6/2004
Mentor Graphics and Artisan Develop High Quality Embedded Memory Testing with Advanced BIST Architecture	10/6/2004
Mentor Graphics Announces Automated Functionality in FastScan and TestKompress DFT Tools	10/5/2004
Mentor Graphics Advances Scalable Verification	10/4/2004
Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models	9/28/2004
Mentor Graphics Offers New Libraries for PADS PCB Design Customers	9/22/2004
Mentor Graphics Announces OASIS Stream File Format Ready for Production	9/14/2004
Mentor Graphics Announces Synthesis Support for Xilinx Virtex-4 FPGAs	9/14/2004
Mentor Graphics Advances Accurate Nanometer Silicon Modeling with New Resistance and Capacitance Engines	9/13/2004
Mentor Graphics and Denali Collaborate to Deliver High-Quality IP for PCI Express and Advanced Switching Interfaces	8/30/2004
Mentor Graphics FastScan ATPG Tool Selected for UMC's 130 and 90 Nanometer Reference Flow	8/25/2004
Mentor's Precision RTL Synthesis Tool Delivers QoR for Designs Using Actel ProASIC Plus Devices	8/24/2004
Mentor Graphics Adds Serial ATA IP with Acquisition of Palmchip IP Business	8/23/2004
Mentor Graphics Releases Enhanced Suite for Electrical Systems Design	8/3/2004
Mentor Graphics Introduces Concurrent Chip-to-Board Solution for FPGA and PCB Design	7/19/2004
Mentor Graphics Introduces DMS2004 Enterprise Library Management	7/14/2004
Mentor Graphics Announces Support for 64-Bit Linux Computing Platforms Based on AMD64 Processors	7/12/2004
Mentor Graphics Offers Technology Design Kit and Design Flow for SMIC 0.18-micron Mixed-Signal Process	7/7/2004
Rambus and Mentor Graphics Collaborate to Offer Interoperable PCI Express Solutions	6/28/2004
UMC Validates the Mentor Graphics Calibre xRC Parasitic Extraction Product for 90nm Process Technology	6/28/2004
GDS-to-OASIS Translator Available as Free Download from Mentor Graphics	6/15/2004
Mentor Graphics Acquires Atair Compiler Technology	6/8/2004
CoWare SPW Supports VHDL Users with Integration of Mentor Graphics' ModelSim Simulator	6/7/2004
Siemens Adopts Mentor Graphics Catapult C Synthesis Tool	5/31/2004
Mentor Graphics Calibre Approved Verification Tool for IBM-Chartered 90nm Design Enablement Platform	5/24/2004
Fujitsu Licenses Mentor Graphics 10 Gigabit Ethernet MAC Solution	5/19/2004
Mentor Graphics Announces the Availability of Calibre on the OpenAccess Database	5/12/2004
Simtek Adopts Calibre xRC for Parasitic Extraction	5/12/2004
Mentor Graphics, X-FAB Provide New Design Kits for Mentor's Mixed-Signal IC Design Flow	4/28/2004
Mentor Updates VStationTBX Verification Accelerator, Delivering Full Language Support for SystemC	4/15/2004
The Mathworks and Mentor Graphics Win EDN Innovation of the Year Award for Link for ModelSim	4/12/2004
MIPS Technologies Verifies Newest 24K Processor Family with Mentor VStationTBX Accelerator	3/29/2004
Mentor Graphics Launches Analysis Tools for Design of Automotive and Aerospace Wiring Systems	3/22/2004
Mentor Graphics Expands Higher Education Program in China to Help Cultivate IC Design Growth	3/9/2004
MIPS Technologies 24K High-Performance Product Line Supported by Mentor Graphics Seamless Co-Verification Tools	2/25/2004
Nassda Announces HSIM Integration with Mentor Graphics ADVance MS Mixed-Signal Simulator	2/17/2004
Mentor Graphics Boosts Scalability of the ADVance MS Mixed-Signal Functional Verification Platform	2/9/2004
Mentor Graphics Collaborates with Intel on PCB Design Kit for Next-Generation Chipset	2/3/2004
Motorola Selects Mentor Graphics TestKompress and Calibre Products for Manufacturing Test and Technology Sign-Off	1/28/2004

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