January 15, 2004 -- In high-performance 90-nanometer designs that are communications-intensive, power has become a hard constraint, and not just in battery-powered devices. High-performance computing chips, broadband processors and networking silicon simply cannot consume more than a certain amount of watts, given the packaging options and energy dissipation characteristics of the system in which they are embedded.
Several trends are compounding this problem. First, leakage power has officially become a first-class component. It can easily exceed a third of total power even for high-activity designs. Although high-performance designs can tolerate more leakage than battery-powered designs, there is a point at which chip yield is leakage-limited. Second, increasing per-chip bandwidth requirements make the power problem more difficult, as communications tend to include large amounts of analog-type components and are often difficult to turn off. Finally, there is a trend toward consolidating design teams, and thus a need to cover an increasingly broad set of requirements (for example, communications standards), which can easily result in a single, energy-inefficient design.
By Juan Antonio Carballo. (Carballo is research staff member at IBM Research.
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
Read more about