January 15, 2004 -- Until recently, predicting IC yield was fairly straightforward: If you could manufacture each structure, you could manufacture the entire chip. The design that was drawn was the one printed on the wafer. The only insight designers had (or needed) into yield issues appeared in design rules with simple DRC yes/no, pass/fail criteria. But as designs have grown more complex, process technologies smaller and geometry counts higher, the work required to achieve acceptable yield has become increasingly demanding and difficult.
At 180 nanometers, newer issues, such as planarity and antennas, began to dominate yield loss. The DRC model was extended to encapsulate them. Now manufacturing has changed even more radically. Long gone are the days of "print as drawn."
By John Ferguson. (Ferguson is product-marketing manager at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
