January 15, 2004 -- A perfect storm of forces-mobility, process technology and system-on-chip complexity-are combining to create a tsunami of challenges for SoC designers who need to manage dynamic power consumption and static leakage at 130- and 90-nm process technologies.
At 130 nm and 90 nm physics begins to work against the designer in regard to power. In previous technology generations, just moving to the lower geometry produced a significant power reduction. Going from 0.25 micron to 0.18 micron lowered the voltage from 2.5 to 1.8 volts, a drop of 0.7 volts. This factor alone could make up for a host of power problems. But future technologies will have voltage levels hovering consistently around 1.2 to 1.0 volts. Changing to a newer technology will provide little benefit to the power budget. Also at 130 and 90, the static or quiescent leakage becomes larger. Thinner gate oxides deliver the speed, but they do so at the price of increased leakage currents. For the foreseeable future process technology will not provide a meaningful solution to the challenge facing power.
By Barry Hoberman. Barry Hoberman is president and chief executive officer of Virtual Silicon Technology, Inc..)
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