January 22, 2004 -- Reducing power dissipation is a dominant concern in battery-backed applications such as cellular phones and PDAs. With a rising trend of system-on-chip die area- sometimes as much as 80 percent-being devoted to memory elements, design techniques for lowering active and standby power are becoming more critical to overall system power reduction.
By Jeremy Brumitt and Cameron Fisher. (Brumitt is senior design engineer and Fisher is director of design engineering at Virage Logic Corp.)
This brief introduction has been excerpted from the original copyrighted article.