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Design and Evaluation of Power-Efficient SoCs  
Publication: Electronic Engineering Times (EE Times)
Contributor: ARM
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January 22, 2004 -- The latest portable devices--from mobile phones to media players--offer a host of new Internet, multimedia and gaming features that place a significant strain on batteries. So the quest to optimize system-wide power use and maximize battery life has led four companies--ARM, Artisan, National and Synopsys--to collaborate on the design of power-saving intellectual property (IP) and systems-on-chip (SoC) that reduce dynamic power consumption based on application software workload, available silicon performance and environmental conditions.

By David Flynn. (Flynn is a fellow in the ARM Ltd.'s Research and Development Group.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Engineering Times (EE Times) website.

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Keywords: Electronic Engineering Times (EE Times), ARM, power analysis, power optimization,
564/4205 1/22/2004 9124 1037


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