This paper details the design of an optimized and robust IO power delivery network for the 400MTS (double pumped 200MHz), 3.2Gbytes/s, AGTL+ Processor-Side Bus (PSB) that links the Intel MCH chipset and the Intel Pentium 4 processor. The MCH package size is minimized through power/ground BGA ball count reduction, while compensating the degraded power delivery through the addition of on package decoupling capacitors.
This optimized power delivery design is derived through
exploring the preferred current return path, and analyzing the power network behavior in both time and frequency domain. Validation results in actual system environments show close correlation with predictions.
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