August 5, 2004 -- All high-speed-digital-product designers face the critical electrical-performance challenges of meeting a timing budget, meeting a noise budget, and passing an EMC (electromagnetic-compliance)-certification test. Designers need to account for a number of factors when calculating a timing budget. Most high-speed, digital products are synchronous, clocked systems, and they require that a series of operations happen within one clock cycle. These operations include all the gate-switching delays within one logic depth, the intrachip propagation delays, the interchip propagation delays, the rise time or charging delays from the interconnections, the setup-and-hold times, and the skews between the clock and the data lines. The timing budget allocates how much time is assigned for each source of delay.
By Eric Bogatin and Gene Garat. (Bogatin is chief technology officer at Synergetix, Inc. Garat is technical marketing engineer for Mentor Graphics' HyperLynx product line.)
This brief introduction has been excerpted from the original copyrighted article.