August 5, 2004 -- Power draw is becoming an increasingly significant factor in overall FPGA power consumption. If you employ FPGAs that are based on SRAM configuration elements, power-up current surges also demand attention. Although the chip vendor's design decisions, rather than yours, define a device's static power consumption, an understanding of static power consumption's root causes can guide your FPGA-technology, vendor, architecture, device, and packaging selections. Accurate power-consumption prediction, before prototype implementation, also enables you to appropriately design your system's power-generation and -distribution subsystems, along with its heat-removal apparatus, thereby maximizing the probability that your system correctly functions the first time you turn it on.

By Brian Dipert, EDN Senior Technical Editor.