August 23, 2004 -- High-speed DSP system designs are becoming increasingly complex due to the DSP's clock speed and potential issues related to signal integrity, power distribution, noise, and electromagnetic radiation.
For these reasons, designers need to understand the importance of the minimum current-return loops and other high-speed phenomena. They must also apply good high-speed design practices to reduce these effects before it's too late. And, future DSP architectures will include wider data buses with more simultaneous switching. This increase will lead to even more transients on DSP power-supply pins, making it critical for engineers to learn how to deal with such problems.
To combat the potential noise, one needs to understand possible sources and their consequences. Today's high-end DSPs have clocks running at 1 GHz, and they send signals through I/O pins at rates approaching 500 MHz.
By Thanh Tran. (Tran is a senior member of the technical staff at Texas Instruments, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Design Magazine website.
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