October 07, 2004 -- For the past five years, the cost of test has prevailed as the hottest topic in test. During this period, automated test equipment (ATE) has made a dramatic move towards low-cost design for test (DFT) testers, and EDA solutions have implemented DFT methods that significantly reduce test data volume and test application time.
Numerous papers have been published on the cost of test and test compression, each of which demonstrates the possibility of marked improvement in reducing test data volume and/or test application time through the introduction of DFT structures on the chip. Now, with numerous test compression technologies at our disposal, we are left with the arduous task of evaluating and choosing the one that is best.
In this paper, we consider the general DFT cost model proposed by Wei and offer a calculated approach to help simplify the evaluation of these different test compression technologies. In this way, we can obtain good data on the relative merits of different compression techniques even if some of the parameters of the detailed model are unknown.
By Rohit Kapur, T.W. Williams, Jennifer Dworak, and M. Ray Mercer. (Kapur is a Synopsys Scientist, Williams is a Synopsys Fellow, Dworak will be joining Brown University as an Assistant Professor, and Mercer is a Professor of Electrical Engineering at Texas A & M University.)
This brief introduction has been excerpted from the original copyrighted article.
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