At 130 nanometers (nm) and below designs that pass physical verification such as design rule checking (DRC) and layout vs. schematic (LVS), may not function as expected due to electrical side effects inherent in nanometer process technology. Therefore, nanometer designs require additional verification before being signed-off for tapeout. For example, the turbulent electrical environment of nanometer processes compromises the integrity of the signals transmitted along the tall, thin wires of nanometer-scale chips. If signal integrity (SI) and other electrical effects are not controlled, a design will likely suffer from lower performance, lower yield, and even functional failure. Any failure identified after the design is manufactured will result in expensive mask changes and delays in getting the chip to market. Consequently, most designs today require a nanometer sign-off process, where the influence of different electrical effects on the functionality and performance of the design are analyzed before tapeout.

A number of nanometer technology advances are responsible for the rise in SI-related chip failures. These include reduced feature sizes, decreases in wire pitch, lower power supply voltages, and shrinking threshold voltages. With each new generation of process technology, more and more levels of wire are packed more closely together. As a consequence, the fraction of total wire capacitance represented by lateral coupling increases dramatically. This in turn is responsible for a dramatic increase in on-chip crosstalk noise. As shown in Figure 1, the number of nets with crosstalk noise levels in excess of 30% of supply voltage more than doubles with each new generation of process technology.