| Magazine & Journal Articles Online |
Featured Online Articles
Boost DFT Efficiency for Large SOCsMentor Graphics Corp.
in Test & Measurement WorldApril 23, 2013 -- One significant design challenge for today's SOCs is managing the impact of the very large design size on EDA tools and flows. Front-end and back-end design flows have managed this challenge by breaking up the design along hierarchical boundaries. The resulting physical cores are then assembled together at the SOC level. This core-based approach to design not only allows EDA tools to run more efficiently but enables multiple design blocks to be completed in parallel, thereby improving overall throughput. The same principles and resulting benefits can be applied towards the design-for-test (DFT) effort as well. . . . read more
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Publications make a wealth of articles about SOC design, EDA tools, intellectual property, ASICs, and programmable logic available online. To save you surfing time, SOCcentral.com regularly scans the leading print and online publications for the most relevant technology, product and industry articles – then abstracts and links to them.
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Articles published online since Wednesday, April 24, 2013 (last 8 weeks) | | The Future of Charge-Trapping Flash Memory (Spansion, Inc. ) in EE Times Memory Designline (6/17/2013) | | Creating Highly Reliable FPGA Designs (Synopsys, Inc. ) in EE Times Programmable Logic Designline (6/13/2013) | | AMBA 5 CHI-based Interconnects Enable Green Datacenter, but Implementers Face Verification and Performance Analysis Challenges (Cadence Design Systems, Inc. ) in Chip Estimate Corp. (6/11/2013) | | Using Non-Volatile Memory IP in System-on-Chip Designs (Kilopass Technology, Inc. ) in EE Times EDA Designline (6/10/2013) | | Scaling NAND Flash to 20-nm Node and Beyond (Micron Technology, Inc. ) in EE Times Memory Designline (6/10/2013) | | 1T-OTP: The Ideal NVM Solution for the Growing Mobile Device Market (Sidense Corp. ) in Chip Estimate Corp. (6/4/2013) | | Address Jitter and Noise More Effectively with DDR4 - Part 2 (Agilent Technologies, Inc. ) in EE Times Memory Designline (5/28/2013) | | Efficient Physical-Aware Timing ECO Solution (ICScape, Inc. ) in EE Times EDA Designline (5/27/2013) | | A Generic DDR Behavioural Model (eInfochips, Ltd. ) in Design & Reuse (5/22/2013) | | Leveraging PCIe SSD Performance with a Full Hardware NVMe (IP-Maker ) in Chip Estimate Corp. (5/21/2013) | | Address Jitter and Noise More Effectively with DDR4 - Part 1 (Agilent Technologies, Inc. ) in EE Times Memory Designline (5/21/2013) | | Automated ECO Flow for Overall Cycle-Time Reduction (Freescale Semiconductor, Inc. ) in Design & Reuse (5/17/2013) | | Building an RTL Sign-off Flow (Real Intent, Inc. ) in Tech Design Forum (5/14/2013) | | Power Verification Is Just as Important as Functional Verification for Complex SOCs (Mentor Graphics Corp. ) in New Electronics Magazine (5/14/2013) | | Customizing SRAM Content to Obtain Truly Differentiated Products (eSilicon Corp. ) in Chip Estimate Corp. (5/14/2013) | | Moving to SystemC TLM for Design and Verification of Digital Hardware (Cadence Design Systems, Inc. ) in EE Times EDA Designline (5/13/2013) | | Understanding On-Board Flash Programming (Micron Technology, Inc. ) in Electronic Design Magazine (5/10/2013) | | Embedded Devices Gird Up Against Cyber Threats in Electronic Design Magazine (5/9/2013) | | Eight Requirements for 3D-IC Design (Cadence Design Systems, Inc. ) in Tech Design Forum (5/8/2013) | | Design Planning for Large SOC Implementation at 40nm: Guaranteeing Predictable Schedule and First-Pass Silicon Success (Open-Silicon, Inc. ) in EDN Magazine (5/7/2013) | | How to Generate Test Patterns to Detect FinFET Defects (Mentor Graphics Corp. ) in Test & Measurement World (5/6/2013) | | Design for Manufacturing and Yield in EDN Magazine (5/6/2013) | | Synthesis-Aware Clock Analysis and Constraints Generation (ICScape, Inc. ) in EE Times EDA Designline (5/6/2013) | | The Power of Developing Hardware and Software in Parallel (Synopsys, Inc. ) in Design & Reuse (5/2/2013) | | Physical Verification of finFET and FD-SOI Devices (Synopsys, Inc. ) in Tech Design Forum (5/2/2013) | | Target Impedance-Based Solutions for Power-Distribution Networks May Not Provide Realistic Assessment in EDN Magazine (5/1/2013) | | Integrating Sensors into Mobile Devices (Sensor Platforms, Inc. ) in ECN Magazine (4/30/2013) | | Tracking Down Interference in Complex RF Environments (Agilent Technologies, Inc. ) in EE Times Militray & Aerospace Highlights (4/30/2013) | | How Small Vendors Compete on Analog IC Market in EE Times Test & Measurement Designline (4/29/2013) | | Simulation Shows How Real Op Amps Can Drive Capacitive Loads (Maxim Integrated Products, Inc. ) in EDN Magazine (4/28/2013) | |
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